S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 281

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8
Analog-to-Digital Converter (ADC12B8CV1)
Block Description
Revision History
8.1
The ADC12B8C is a 8-channel, 12-bit, multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ATD accuracy.
8.1.1
Freescale Semiconductor
Number
Version
V01.00
V01.01
V01.02
V01.03
V01.04
•
•
•
•
•
•
•
•
•
•
•
8-, 10-, or 12-bit resolution.
Conversion in Stop Mode using internally generated clock
Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value
Programmable sample time.
Left/right justified result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 8 analog input channels.
Special conversions for V
1-to-8 conversion sequence lengths.
Introduction
14 Sept 2007
25 July 2007
30 Apr 2008
1 Oct 2007
9 Oct 2007
Revision
Features
Date
14 Sept 2007
25 July 2007
30 Apr 2008
1 Oct 2007
9 Oct 2007
Effective
Date
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
RH
, V
RL
Author
, (V
RL
+V
RH
Initial version
Added reserved registers at the end the memory map.
Added following mention where applies:
(n conversion number, NOT channel number!)
Modified table “Analog Input Channel Select Coding” due to
new customer feature (SPECIAL17).
Updated document for 8 channels.
)/2.
Description of Changes
281