HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 16

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.6 Usage Notes ...................................................................................................................... 211
Section 11 Multi-Function Timer Pulse Unit (MTU)........................................213
11.1 Features............................................................................................................................. 213
11.2 Input/Output Pins .............................................................................................................. 217
11.3 Register Descriptions ........................................................................................................ 218
11.4 Operation .......................................................................................................................... 259
11.5 Interrupt Sources............................................................................................................... 310
Rev.4.00 Mar. 27, 2008 Page xiv of xliv
REJ09B0108-0400
10.5.2 Example of DMA Transfer between External RAM and External Device
10.5.3 Example of DMA Transfer between A/D Converter and On-chip Memory
10.5.4 Example of DMA Transfer between External Memory and SCI1 Transmit Side
11.3.1 Timer Control Register (TCR)............................................................................. 220
11.3.2 Timer Mode Register (TMDR) ............................................................................ 224
11.3.3 Timer I/O Control Register (TIOR) ..................................................................... 226
11.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 244
11.3.5 Timer Status Register (TSR)................................................................................ 246
11.3.6 Timer Counter (TCNT)........................................................................................ 249
11.3.7 Timer General Register (TGR) ............................................................................ 249
11.3.8 Timer Start Register (TSTR) ............................................................................... 250
11.3.9 Timer Synchronous Register (TSYR).................................................................. 250
11.3.10 Timer Output Master Enable Register (TOER) ................................................... 252
11.3.11 Timer Output Control Register (TOCR) .............................................................. 253
11.3.12 Timer Gate Control Register (TGCR) ................................................................. 255
11.3.13 Timer Subcounter (TCNTS) ................................................................................ 257
11.3.14 Timer Dead Time Data Register (TDDR)............................................................ 257
11.3.15 Timer Period Data Register (TCDR) ................................................................... 257
11.3.16 Timer Period Buffer Register (TCBR)................................................................. 257
11.3.17 Bus Master Interface ............................................................................................ 258
11.4.1 Basic Functions.................................................................................................... 259
11.4.2 Synchronous Operation........................................................................................ 264
11.4.3 Buffer Operation .................................................................................................. 266
11.4.4 Cascaded Operation ............................................................................................. 269
11.4.5 PWM Modes ........................................................................................................ 271
11.4.6 Phase Counting Mode .......................................................................................... 276
11.4.7 Reset-Synchronized PWM Mode......................................................................... 282
11.4.8 Complementary PWM Mode............................................................................... 285
11.5.1 Interrupt Sources and Priorities............................................................................ 310
with DACK .......................................................................................................... 207
(Address Reload On)............................................................................................ 208
(Indirect Address On) .......................................................................................... 210