HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 459

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
3
Bit Name Initial Value R/W
PER
0
R/(W)* Parity Error
Description
Indicates that a parity error occurred during reception
using parity addition in asynchronous mode, causing
abnormal termination.
[Setting condition]
•
If a parity error occurs, the receive data is transferred to
RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the PER flag
is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing conditions]
•
•
The PER flag is not affected and retains its previous
state even if the RE bit in SCR is cleared to 0.
When a parity error is detected during reception
Power-on reset or software standby mode
When 0 is written to PER after reading PER = 1
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 413 of 882
REJ09B0108-0400