HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 227

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 10.2 is a flowchart of this procedure.
(SAR, DAR, DMATCR, CHCR, DMAOR)
DEI interrupt request (when IE = 1)
DMATCR – 1 → DMATCR,
Notes:
Transfer (1 transfer unit);
SAR and DAR updated
NMIF, AE, TE = 0?
NMIF = 1, AE = 1,
DE, DME = 1 and
Transfer request
DE = 0, or DME
DMATCR = 0?
Initial settings
Transfer ends
Yes
Yes
occurs?*
Yes
Yes
1.
2.
3.
Start
Does
= 0?
Figure 10.2 DMAC Transfer Flowchart
In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,
and the DE and DME bits are set to 1.
DREQ = level detection in burst mode (external request) or cycle-steal
mode.
DREQ = edge detection in burst mode (external request), or auto-request
mode in burst mode.
1
No
No
No
No
NMIF = 1, AE = 1,
Transfer aborted
DE = 0, or DME
10. Direct Memory Access Controller (DMAC)
Normal end
Yes
*
Does
= 0?
3
Rev.4.00 Mar. 27, 2008 Page 181 of 882
DREQ detection selection
transfer request mode,
Bus mode,
system
No
*
2
REJ09B0108-0400