HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 193

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.5.2
BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal
assert extension of each CS space.
Bit
15
14
13
12
Bit Name Initial Value R/W
IW31
IW30
IW21
IW20
Bus Control Register 2 (BCR2)
1
1
1
1
R/W
R/W
R/W
R/W
Description
Idle cycles in CS3 and CS7 space cycles
After read access to the CS3 and CS7 spaces, these bits
insert idle cycles (1) when the write cycle to the CS3
space continues, (2) when the write cycle to the CS7
space continues, or (3) when continuous access is made
to CS spaces except for the CS3 and CS7 spaces.
00: No idle cycle inserted after access to the CS3 and
01: One idle cycle inserted after access to the CS3 and
10: Two idle cycles inserted after access to the CS3 and
11: Three idle cycles inserted after access to the CS3
Idle cycles in CS2 and CS6 space cycles
After read access to the CS2 and CS6 spaces, these bits
insert idle cycles (1) when the write cycle to the CS2
space continues, (2) when the write cycle to the CS6
space continues, or (3) when continuous access is made
to CS spaces except for the CS2 and CS6 spaces.
00: No idle cycle inserted after access to the CS2 and
01: One idle cycle inserted after access to the CS2 and
10: Two idle cycles inserted after access to the CS2 and
11: Three idle cycles inserted after access to the CS2
and CS6 spaces
and CS7 spaces
CS7 spaces
CS7 spaces
CS7 spaces
CS6 spaces
CS6 spaces
CS6 spaces
Rev.4.00 Mar. 27, 2008 Page 147 of 882
9. Bus State Controller (BSC)
REJ09B0108-0400