HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 355

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Complementary PWM Mode Output Protection Function:
Complementary PWM mode output has the following protection functions.
1. Register and counter miswrite prevention function
2. Halting of PWM output by external signal
3. Halting of PWM output when oscillator is stopped
With the exception of the buffer registers, which can be rewritten at any time, access by the
CPU can be enabled or disabled for the mode registers, control registers, compare registers,
and counters used in complementary PWM mode by means of the MTURWE bit in the bus
controller’s bus control register 1 (BCR1). The applicable registers are some (21 in total) of the
registers in channels 3 and 4 shown in the following:
⎯
This function enables miswriting due to CPU runaway to be prevented by disabling CPU
access to the mode registers, control registers, and counters. When the applicable registers are
read in the access-disabled state, undefined values are returned. Writing to these registers is
ignored.
The 6-phase PWM output pins can be set automatically to the high-impedance state by
inputting specified external signals. There are four external signal input pins.
See section 11.9, Port Output Enable (POE), for details.
If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins
automatically go to the high-impedance state. The pin states are not guaranteed when the clock
is restarted.
See section 4.2, Function for Detecting Oscillator Halt.
TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3
and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR.
TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and
11.
Rev.4.00 Mar. 27, 2008 Page 309 of 882
Multi-Function Timer Pulse Unit (MTU)
REJ09B0108-0400