HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 89

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• System Control Instructions
Instruction
CLRT
CLRMAC
LDC
LDC
LDC
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS
LDS
LDS
LDS.L @Rm+,MACH 0100mmmm00000110
LDS.L @Rm+,MACL 0100mmmm00010110
LDS.L @Rm+,PR
NOP
RTE
SETT
SLEEP
STC
STC
STC
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STS
STS
STS
STS.L MACH,@–Rn 0100nnnn00000010
STS.L MACL,@–Rn 0100nnnn00010010
STS.L PR,@–Rn
Rm,SR
Rm,GBR
Rm,VBR
Rm,MACH
Rm,MACL
Rm,PR
SR,Rn
GBR,Rn
VBR,Rn
MACH,Rn
MACL,Rn
PR,Rn
Instruction Code
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00100110
0000000000001001
0000000000101011
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00100010
Operation
0 → T
0 → MACH, MACL
Rm → SR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
No operation
Delayed branch, stack area
→ PC/SR
1 → T
Sleep
SR → Rn
GBR → Rn
VBR → Rn
Rn – 4 → Rn, SR → (Rn)
Rn – 4 → Rn, GBR → (Rn)
Rn – 4 → Rn, BR → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
Rn – 4 → Rn, MACH → (Rn)
Rn – 4 → Rn, MACL → (Rn)
Rn – 4 → Rn, PR → (Rn)
Rev.4.00 Mar. 27, 2008 Page 43 of 882
REJ09B0108-0400
Execution
States
1
1
1
1
1
3
3
3
1
1
1
1
1
1
1
4
1
3*
1
1
1
2
2
2
1
1
1
1
1
1
2. CPU
T Bit
0
—
LSB
—
—
LSB
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—