HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 81

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
• Instruction Code Format
Notes: 1. Instruction execution states: The execution states shown in the table are minimums.
Item
Instruction
Instruction
code
Outline of the
Operation
Execution
states
T bit
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
The actual number of states may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) equals to the register used by the next instruction.
refer the SH-1/SH-2/SH-DSP Software Manual.
Format
Described in
mnemonic.
OP.Sz SRC,DEST
Described in MSB ↔
LSB order
→, ←
(xx)
M/Q/T
&
|
^
~
<<n
>>n
—
—
Explanation
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Direction of transfer
Memory operand
Flag bits in the SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit left shift
n-bit right shift
Value when no wait states are inserted*
Value of T bit after instruction is executed. An em-dash (—)
in the column means no change.
0000: R0
0001: R1
1111: R15
⋅
⋅
⋅
Rev.4.00 Mar. 27, 2008 Page 35 of 882
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