HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 543

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 14.7 Example: Flowchart of Operations in the Master Transmit Mode
No
Write data for transmission to ICDR
No
No
No
Clear the IRIC flag in ICCR
Read the BBSY flag in ICCR
Read the ACKB bit in ICSR
No
Write transmit data to ICDR
Read the ACKB bit in ICSR
Read the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Write 0 to the ACKE bit
and TRS = 1 (ICCR)
and SCP = 0 (ICCR)
and SCP = 0 (ICCR)
Transmit mode?
Write BBSY = 0
Write BBSY= 1
Initial setting
Transmission
BBSY = 0?
ACKB = 0?
(ACKB = 1?)
Set MST = 1
completed?
IRIC = 1?
IRIC = 1?
IRIC = 1?
in ICCR
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1] Initial setting
[2] Determine the states of the SCL and SDA lines.
[3] Set master transmit mode
[4] Start condition issuance
[5] Wait for the start condition generation
[6] Set transmit data for the first byte (slave address + R/ W)
[7] Wait for 1 byte to be transmitted.
[8] Determine the acknowledge bit transferred from the
[9] Set transmit data for the second and subsequent bytes.
[10] Wait for 1 byte to be transmitted.
[11] Determine the end of transfer
[12] Stop condition issua
Master receive mode
(After writing to ICDR, clear IRIC sequentially)
specified slave device.
(After writing to ICDR, clear IRIC sequentially)
Rev.4.00 Mar. 27, 2008 Page 497 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400