HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 256

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10. Direct Memory Access Controller (DMAC)
10.5.4
In this example, DMAC channel 3 is used, an indirect address designated external memory is the
transfer source and the SCI1 transmit side is the transfer destination.
Table 10.10 indicates the transfer conditions and the setting values of each of the registers.
Table 10.10 Transfer Conditions and Register Set Values for Transfer between External
When indirect address mode is on, the data stored in the address established in SAR is not used as
the transfer source data. In the case of indirect addressing, the value stored in the SAR address is
read, then that value is used as the address and the data read from that address is used as the
transfer source data, then that data is stored in the address designated by the DAR.
In the table 10.10 example, when a transfer request from the TDR_1 of SCI_1 is generated, a read
of the address located at H'00400000, which is the value set in SAR_3, is performed first. The data
H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000
value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is
stored in the H'00450000 address. It then writes the value H'55 to the address H'FFFF81B3
designated by DAR_3 to complete one indirect address transfer.
Rev.4.00 Mar. 27, 2008 Page 210 of 882
REJ09B0108-0400
Transfer Conditions
Transfer source: external memory
Value stored in address H'00400000
Value stored in address H'00450000
Transfer destination: on-chip SCI1 (TDR1)
Transfer count: 10 times
Transfer source address: incremented
Transfer destination address: fixed
Transfer request source: SCI1 (TDR1)
Bus mode: cycle steal
Transfer unit: byte
Interrupt request not generated at end of transfer
Channel priority ranking: 0 > 1 > 2 > 3
Example of DMA Transfer between External Memory and SCI1 Transmit Side
(Indirect Address On)
Memory and SCI1 Transmit Side
Register
SAR_3
—
—
DAR_3
DMATCR_3
CHCR_3
DMAOR
Value
H'00400000
H'00450000
H'55
H'FFFF81B3
H'0000000A
H'00011E01
H'0001