HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 735

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
This LSI is available with 256 kbytes of on-chip mask ROM. The on-chip ROM is connected to
the CPU, direct memory access controller (DMAC), and data transfer controller (DTC) through a
32-bit data bus (figure 20.1). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16
and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
The operating mode determines whether the on-chip ROM is valid or not. The operating mode is
selected using mode-setting pins FWP and MD3-MD0 as shown in table 3.1. If you are using the
on-chip ROM, select mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is
allocated to addresses H'00000000 to H'0003FFFF of memory area 0.
20.1
• Module Standby Mode Setting
Access to the on-chip ROM can be enabled/disabled by the module standby control register
(MSTCR1). The initial value enables the on-chip ROM operation. On-chip ROM access is
disabled by setting the module standby mode. For details, see section 24, Power-Down Modes.
Usage Note
H'0003FFFC
H'00000000
H'00000004
Figure 20.1 Mask ROM Block Diagram
Section 20 Mask ROM
H'0003FFFD
H'00000001
H'00000005
Internal data bus (32 bits)
On-chip ROM
H'0003FFFE
H'00000002
H'00000006
Rev.4.00 Mar. 27, 2008 Page 689 of 882
H'0003FFFF
H'00000003
H'00000007
REJ09B0108-0400
20. Mask ROM

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