HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 217

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.3.2
DMA destination address registers_0 to 3 (DAR_0 to DAR_3) are 32-bit readable/writable
registers that specify the destination address of a DMA transfer. These registers have a count
function, and during a DMA transfer, they indicate the next destination address. In single-address
mode, DAR values are ignored when a device with DACK has been specified as the transfer
destination.
Specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. Operation
cannot be guaranteed on any other address. When this register is accessed in 16 bits, the value of
another 16 bits that are not accessed is retained.
The initial value of DAR is undefined.
10.3.3
DMA transfer count registers_0 to 3 (DMATCR_0 to DMATCR_3) are 32-bit readable/writable
registers that specify the transfer count for each channel (byte count, word count, or longword
count) with lower 24 bits. Specifying a H'000001 gives a transfer count of 1, while H'000000
gives the maximum setting, 16,777,216 transfers. While DMAC is in operation, the number of
transfers to be performed is indicated.
Upper eight bits of this register are read as 0 and the write value should always be 0. When this
register is accessed in 16 bits, the value of another 16 bits that are not accessed is retained.
The initial value of DMATCR is undefined.
DMA Destination Address Registers_0 to 3 (DAR_0 to DAR_3)
DMA Transfer Count Registers_0 to 3 (DMATCR_0 to DMATCR_3)
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 171 of 882
REJ09B0108-0400