HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 756

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23. Advanced User Debugger (AUD)
23.3
23.3.1
In this mode, the branch destination address is output when a branch occurs in the user program.
Branches may be caused by branch instruction execution or interrupt/exception processing, but no
distinction is made between the two in this mode.
23.3.2
Operation starts in branch trace mode when AUDRST is asserted, AUDMD is driven low, and
then AUDRST is negated.
Figure 23.2 shows an example of data output.
While the user program is being executed without branches, the AUDATA pins constantly output
0011 in synchronization with AUDCK.
When a branch occurs, after execution starts at the branch destination address in the PC, the
previous fully output address (i.e. for which output was not interrupted by the occurrence of
another branch) is compared with the current branch address, and depending on the result,
AUDSYNC is asserted and the branch destination address output after 1-clock output of 1000 (in
the case of 4-bit output), 1001 (8-bit output), 1010 (16-bit output), or 1011 (32-bit output). The
initial value of the compared address is H'00000000.
On completion of the cycle in which the address is output, AUDSYNC is negated and 0011 is
simultaneously output from the AUDATA pins.
If another branch occurs during branch destination address output, the later branch has priority for
output. In this case, AUDSYNC is negated and the AUDATA pins output the address after
outputting 10xx again (figure 23.3 shows an example of the output when consecutive branches
occur). Note that the compared address is the previous fully output address, and not an interrupted
address (since the upper address of an interrupted address will be unknown).
The interval from the start of execution at the branch destination address in the PC until the
AUDATA pins output 10xx is 1.5 or 2 AUDCK cycles.
Rev.4.00 Mar. 27, 2008 Page 710 of 882
REJ09B0108-0400
Branch Trace Mode
Overview
Operation