HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 448

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface (SCI)
Note: etu (Elementary Time Unit): Abbreviation for the transfer period for one bit.
13.3.6
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 13.8, Interrupt Sources. Some bit functions of SCR differ between normal serial
communication interface mode and smart card interface mode.
• Normal serial communication interface mode (when SMIF in SDCR is 0)
Rev.4.00 Mar. 27, 2008 Page 402 of 882
REJ09B0108-0400
Bit
1
0
Bit
7
6
Bit Name
TIE
RIE
Bit Name Initial Value R/W
CKS1
CKS0
Serial Control Register (SCR)
0
0
0
0
Initial Value
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 1 and 0
These bits select the clock source for the on-chip baud
rate generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10: Pφ/32 clock (n = 2)
11: Pφ/128 clock (n = 3)
For details on the relationship between the setting of
these bits and the baud rate, refer to section 13.3.9, Bit
Rate Register (BRR). n is the decimal representation of
the value of n in BRR (see section 13.3.9, Bit Rate
Register (BRR)).
Description
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
TXI interrupt request cancellation can be performed
by reading 1 from the TDRE flag in SSR, then
clearing it to 0, or clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF, FER, PER,
or ORER flag in SSR, then clearing the flag to 0, or
clearing the RIE bit to 0.