HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 427

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.3
The WDT has the following three registers. For details, see section 25, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method
different from normal registers. For details, see section 12.6.1, Notes on Register Access.
• Timer control/status register (TCSR)
• Timer counter (TCNT)
• Reset control/status register (RSTCSR)
12.3.1
TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected
by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows
(changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer
interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR.
The initial value of TCNT is H'00.
Register Descriptions
Timer Counter (TCNT)
Rev.4.00 Mar. 27, 2008 Page 381 of 882
12. Watchdog Timer
REJ09B0108-0400