MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 129

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.2.2 PWM Clock Select and Polarity Register
Read: Anytime
Write: Anytime
PCLK3 — PWM Channel 3 Clock Select Bit
PCLK2 — PWM Channel 2 Clock Select Bit
PCLK1 — PWM Channel 1 Clock Select Bit
PCLK0 — PWM Channel 0 Clock Select Bit
PPOL3 — PWM Channel 3 Polarity Bit
PPOL2 — PWM Channel 2 Polarity Bit
PPOL1 — PWM Channel 1 Polarity Bit
PPOL0 — PWM Channel 0 Polarity Bit
Depending on the polarity bit, the duty registers may contain the count of either the high time or the low
time. If the polarity bit is 0 and left alignment is selected, the duty registers contain a count of the low time.
If the polarity bit is 1, the duty registers contain a count of the high time.
Freescale Semiconductor
If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse may
occur during the transition.
0 = Clock B is the clock source for channel 3.
1 = Clock S1 is the clock source for channel 3.
0 = Clock B is the clock source for channel 2.
1 = Clock S1 is the clock source for channel 2.
0 = Clock A is the clock source for channel 1.
1 = Clock S0 is the clock source for channel 1.
0 = Clock A is the clock source for channel 0.
1 = Clock S0 is the clock source for channel 0.
0 = Channel 3 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 3 output is high at the beginning of the period, low when the duty count is reached.
0 = Channel 2 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 2 output is high at the beginning of the period, low when the duty count is reached.
0 = Channel 1 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 1 output is high at the beginning of the period, low when the duty count is reached.
0 = Channel 0 output is low at the beginning of the period, high when the duty count is reached.
1 = Channel 0 output is high at the beginning of the period, low when the duty count is reached.
Address: $0041
Reset:
Read:
Write:
Figure 11-5. PWM Clock Select and Polarity Register (PWPOL)
PCLK3
Bit 7
0
PCLK2
6
0
M68HC12B Family Data Sheet, Rev. 9.1
PCLK1
5
0
PCLK0
4
0
PPOL3
3
0
PPOL2
2
0
PPOL1
1
0
PWM Register Descriptions
PPOL0
Bit 0
0
129