MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 198

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Interface
14.2.3.4 SCI Status Register 1
Read: Anytime; used in auto clearing mechanism
Write: Has no meaning or effect
The bits in these registers are set by various conditions in the SCI hardware and are cleared automatically
by special acknowledge sequences. The receive related flag bits in SC0SR1 (RDRF, IDLE, OR, NF, FE,
and PF) are all cleared by a read of the SC0SR1 register followed by a read of the transmit/receive data
register low byte. However, only those bits which were set when SC0SR1 was read will be cleared by the
subsequent read of the transmit/receive data register low byte. The transmit related bits in SC0SR1
(TDRE and TC) are cleared by a read of the SC0SR1 register followed by a write to the transmit/receive
data register low byte.
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
198
New data is not transmitted unless SC0SR1 is read before writing to the transmit data register. Reset
sets this bit.
Flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
by reading SC0SR1 with TC set and then writing to SC0DR.
Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. RDRF
is set if a received character is ready to be read from SC0DR. Clear the RDRF flag by reading SC0SR1
with RDRF set and then reading SC0DR.
Receiver idle line is detected (the receipt of a minimum of 10 or 11 consecutive 1s). This bit is not set
by the idle line condition when the RWU bit is set. Once cleared, IDLE is not set again until after RDRF
has been set (after the line has been active and becomes idle again).
0 = SC0DR busy
1 = Any byte in the transmit data register is transferred to the serial shift register so new data may
0 = Transmitter busy
1 = Transmitter idle
0 = SC0DR empty
1 = SC0DR full
0 = RxD line active
1 = RxD line idle
now be written to the transmit data register.
Address:
Reset:
Read:
Write:
$00C4
TDRE
Bit 7
1
Figure 14-7. SCI Status Register 1 (SC0SR1)
= Unimplemented
TC
M68HC12B Family Data Sheet, Rev. 9.1
6
1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Freescale Semiconductor
Bit 0
PF
0