MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 246

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

msCAN12 Controller
to release the foreground buffer. A new message, which can follow immediately after the IFS field of the
CAN frame, is received into RxBG. The over-writing of the background buffer is independent of the
identifier filter function.
When the msCAN12 module is transmitting, the msCAN12 receives its own messages into the
background receive buffer, RxBG, but does not overwrite RxFG, generate a receive interrupt, or
acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see
16.12.2 msCAN12 Module Control Register
1) where the msCAN12 treats its own messages exactly like
all other incoming messages. The msCAN12 receives its own transmitted messages in the event that it
loses arbitration. If arbitration is lost, the msCAN12 must be prepared to become the receiver.
An overrun condition occurs when both the foreground and the background receive message buffers are
filled with correctly received messages with accepted identifiers and another message is correctly
received from the bus with an accepted identifier. The latter message is discarded and an error interrupt
with overrun indication is generated if enabled. The msCAN12 is still able to transmit messages with both
receive message buffers filled, but all incoming messages are discarded.
16.3.3 Transmit Structures
The msCAN12 has a triple transmit buffer scheme to allow multiple messages to be set up in advance
and to achieve an optimized real-time performance. The three buffers are arranged as shown in
Figure
16-2.
All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see
16.11
Programmer’s Model of Message
Storage). An additional transmit buffer priority register (TBPR) contains
an 8-bit local priority field (PRIO). See
16.11.5 Transmit Buffer Priority
Register.
To transmit a message, the CPU12 has to identify an available transmit buffer which is indicated by a set
transmit buffer empty (TXE) flag in the msCAN12 transmitter flag register (CTFLG). See
16.12.7
msCAN12 Transmitter Flag
Register.
The CPU12 then stores the identifier, the control bits, and the data content into one of the transmit buffers.
Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag.
The msCAN12 then will schedule the message for transmission and will signal the successful
(1)
transmission of the buffer by setting the TXE flag. A transmit interrupt will be emitted
when TXE is set,
and this can be used to drive the application software to reload the buffer.
If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration,
the msCAN12 uses the local priority setting of the three buffers for prioritizing. For this purpose, every
transmit buffer has an 8-bit local priority field (PRIO). The application software sets this field when the
message is set up. The local priority reflects the priority of this particular message relative to the set of
messages being emitted from this node. The lowest binary value of the PRIO field is defined to be the
highest priority.
The internal scheduling process takes place whenever the msCAN12 arbitrates for the bus. This is also
the case after the occurrence of a transmission error.
1. Only if the RXF flag is not set
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
1. The transmit interrupt is generated only if not masked. A polling scheme can be applied on TXE also.
M68HC12B Family Data Sheet, Rev. 9.1
246
Freescale Semiconductor