MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 29

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

selectable (interrupt control register, INTCR). IRQ is always configured to level-sensitive triggering at
reset. When the MCU is reset, the IRQ function is masked in the condition code register.
This pin is always an input and can always be read. In special modes, it can be used to apply external
EEPROM V
and erase cycles. Because the IRQ pin is also used as an EEPROM programming voltage pin, there is
an internal resistive pullup on the pin.
1.6.3.5 XIRQ
XIRQ is the non-maskable external interrupt pin. It provides a means of requesting a non-maskable
interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any
interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be
connected to a multiple-source wired-OR network. This pin is always an input and can always be read.
There is an active pullup on this pin while in reset and immediately out of reset. The pullup can be turned
off by clearing the PUPE bit in the pullup control register (PUCR). XIRQ is often used as a power loss
detect interrupt.
When XIRQ or IRQ are used with multiple interrupt sources (IRQ must be configured for level-sensitive
operation if there is more than one source of IRQ interrupt), each source must drive the interrupt input
with an open-drain type of driver to avoid contention between outputs. There must also be an interlock
mechanism at each interrupt source so that the source holds the interrupt line low until the MCU
recognizes and acknowledges the interrupt request. If the interrupt line is held low, the MCU recognizes
another interrupt as soon as the interrupt mask bit in the MCU is cleared, normally upon return from an
interrupt.
1.6.3.6 SMODN, MODA, and MODB
SMODN, MODA, and MODB are the mode-select signals. Their state during reset determines the MCU
operating mode. After reset, MODA and MODB can be configured as instruction queue tracking signals
IPIPE0 and IPIPE1. MODA and MODB have active pulldowns during reset.
The SMODN pin can be used as BKGD or TAGHI after reset.
1.6.3.7 BKGD
BKGD is the single-wire background mode pin. It receives and transmits serial background debugging
commands. A special self-timing protocol is used. The BKGD pin has an active pullup when configured
as input; BKGD has no pullup control. Currently, the tool connection configuration shown in
used.
Freescale Semiconductor
PP
in support of EEPROM testing. External V
To aid in mode selection, refer to
schematics are provided as suggestive layouts only.
Figure 1-7. BDM Tool Connector
M68HC12B Family Data Sheet, Rev. 9.1
BKGD
V
NC
FP
1
3
5
Figure 1-8
NOTE
2
4
6
PP
GND
RESET
V
DD
and
is not needed for normal EEPROM program
Figure
1-9. These
Pinout and Signal Descriptions
Figure 1-7
is
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