MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 267

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RERRIF — Receiver Error Passive Interrupt Flag
TERRIF — Transmitter Error Passive Interrupt Flag
BOFFIF — Bus-Off Interrupt Flag
OVRIF — Overrun Interrupt Flag
RXF — Receive Buffer Full Flag
1. Condition to set the flag: RERRIF = (128 ≤ REC ≤ 255) & BOFFIF
2. Condition to set the flag: TERRIF = (128 ≤ TEC ≤ 255) & BOFFIF
Freescale Semiconductor
This flag is set when the msCAN12 goes into error passive status due to the receive error counter
(REC) exceeding 127 and the bus-off interrupt flag is not set
pending while this flag is set.
This flag is set when the msCAN12 goes into error passive status due to the transmit error counter
(TEC) exceeding 127 and the bus-off interrupt flag is not set
pending while this flag is set.
This flag is set when the msCAN12 goes into bus-off status, due to the transmit error counter
exceeding 255. It cannot be cleared before the msCAN12 has monitored 128 times 11 consecutive
recessive bits on the bus. If not masked, an error interrupt is pending while this flag is set.
This flag is set when a data overrun condition occurs. If not masked, an Error interrupt is pending while
this flag is set.
The RXF flag is set by the msCAN12 when a new message is available in the foreground receive
buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the
CPU has read that message from the receive buffer, the RXF flag must be handshaken (cleared) to
release the buffer. A set RXF flag prohibits the exchange of the background receive buffer into the
foreground buffer. If not masked, a receive interrupt is pending while this flag is set.
0 = No receiver error passive status has been reached.
1 = msCAN12 went into receiver error passive status.
0 = No transmitter error passive status has been reached.
1 = msCAN12 went into transmitter error passive status.
0 = No bus-off status has been reached.
1 = msCAN12 went into bus-off status.
0 = No data overrun has occurred.
1 = A data overrun has been detected.
0 = Receive buffer is released (not full).
1 = Receive buffer is full. A new message is available.
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.The CRFLG register is held in the reset state
when the SFTRES bit in CMCR0 is set.
M68HC12B Family Data Sheet, Rev. 9.1
NOTE
(2)
(1)
. If not masked, an error interrupt is
. If not masked, an error interrupt is
Programmer’s Model of Control Registers
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