MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 235

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TSIFR — Transmit Single Byte IFR with No CRC Bit (Type 1 and Type 2)
Freescale Semiconductor
The BDLC supports the in-frame response (IFR) features of J1850. The four types of J1850 IFR are
shown in
The purpose of the in-frame response modes is to allow multiple nodes to acknowledge receipt of the
data by responding with their personal ID or physical address in a concatenated manner after they
have seen the EOD symbol. If transmission arbitration is lost by a node while sending its response, it
continues to transmit its ID/address until observing its unique byte in the response stream. For VPW
modulation, the first bit of the IFR is always passive; therefore, an active normalization bit must be
generated by the responder and sent prior to its ID/address byte. When there are multiple responders
on the J1850 bus, only one normalization bit is sent which assists all other transmitting nodes to sync
their responses.
The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as a
single byte IFR with no CRC. Typically, the byte transmitted is a unique identifier or address of the
transmitting (responding) node. See
If the programmer attempts to set the TSIFR bit immediately after the EOD symbol has been received
from the bus, the TSIFR bit remains in the reset state and no attempt is made to transmit the IFR byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and after the IFR byte winning
arbitration completes transmission, the BDLC again attempts to transmit the BDR (with no
normalization bit). The BDLC continues transmission attempts until an error is detected on the bus, or
TEOD is set, or the BDLC transmission is successful.
If loss of arbitration occurs in the last bit of the IFR byte, two additional 1 bits are not sent out because
the BDLC attempts to retransmit the byte in the transmit shift register after the IRF byte winning
arbitration completes transmission.
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
0 = TSIFR bit is cleared automatically, once the BDLC has successfully transmitted the byte in the
TYPE 1 — SINGLE BYTE FROM A SINGLE RESPONDER
TYPE 2 — SINGLE BYTE FROM MULTIPLE RESPONDERS
TYPE 0 — NO IFR
TYPE 3 — MULTIPLE BYTES FROM A SINGLE RESPONDER
has been received the BDLC attempts to transmit the appropriate normalization bit followed by
the byte in the BDR.
BDR onto the bus, or TEOD is set, or an error is detected on the bus.
Figure
HEADER
HEADER
HEADER
HEADER
15-14.
Figure 15-14. Types of In-Frame Response
DATA FIELD
DATA FIELD
DATA FIELD
DATA FIELD
M68HC12B Family Data Sheet, Rev. 9.1
Figure
15-14.
CRC
CRC
CRC
CRC
NB
NB
NB
ID1
ID
IFR DATA FIELD
IDn
CRC
BDLC Registers
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