MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 284

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Analog-to-Digital Converter (ATD)
17.3.7 ATD Status Registers
Read: Normally anytime
Write: In special mode, the SCF bit and the CCF bits may also be written.
The ATD status registers contain the flags indicating the completion of ATD conversions.
SCF — Sequence Complete Flag
284
This bit is set at the end of the conversion sequence when in the single conversion sequence mode
(SCAN = 0 in ATDCTL5) and is set at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is cleared when a write is performed
to ATDCTL5 to initiate a new conversion sequence. When AFFC = 1, SCF is cleared after the first
result register is read.
Table 17-4. Multichannel Mode Result Register Assignment (Continued) (Continued)
S8CM
Address: $0066
Address: $0067
Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight channels makes
Reset:
Reset:
1
Read:
Read:
Write:
Write:
up a conversion sequence. When MULT = 0, all four bits (CD, CC, CB, and CA) must be
specified and a conversion sequence consists of four or eight consecutive conversions of
the single specified channel.
CD
1
CCF7
Bit 7
SCF
Bit 7
0
0
Figure 17-9. ATD Status Register (ATDSTAT)
CC
0
0
0
0
1
1
1
1
= Unimplemented
CCF6
6
0
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
CB
0
0
1
1
0
0
1
1
CCF5
CA
0
1
0
1
0
1
0
1
5
0
0
5
0
Figure 17-8
CCF4
4
0
0
4
0
Channel Signal
(V
Test/reserved
Reserved
Reserved
Reserved
Reserved
RH
V
V
+ V
CCF3
RH
RL
3
0
0
3
0
RL
)/2
CCF2
CC2
2
0
2
0
Result in ADRx
CCF1
if MULT = 1
CC1
1
0
1
0
ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
Freescale Semiconductor
CCF0
Bit 0
CC0
Bit 0
0
0