MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 231

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The BDLC cannot transmit a BREAK symbol. It can receive a BREAK symbol only from the J1850 bus.
15.8.5.5 Summary
Table 15-1
15.9 BDLC Registers
Eight registers are available for controlling operation of the BDLC and for communicating data and status
information. A full description of each register is given here.
15.9.1 BDLC Control Register 1
IMSG — Ignore Message Bit
Freescale Semiconductor
Transmission error
Cyclical redundancy check
(CRC) error
Invalid symbol: BDLC transmits,
but receives invalid bits (noise)
Framing error
Bus short to V
Bus short to GND
BDLC receives BREAK symbol
This bit disables the receiver until a new start-of-frame (SOF) is detected. The bit is cleared
automatically by the reception of an SOF symbol or a BREAK symbol. It then generates interrupt
requests and allows changes of the status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit. When set, all BDLC interrupt requests are masked (except $20
in BSVR) and the status bits are held in their reset state. If this bit is set while the BDLC is receiving a
message, the rest of the incoming message is ignored.
1 = Disable receiver
0 = Enable receiver
Error Condition
provides a bus error summary.
DD
Address: $00F8
Reset:
Read:
Write:
IMSG
Bit 7
R
1
Figure 15-12. BDLC Control Register 1 (BCR1)
Table 15-1. BDLC J1850 Bus Error Summary
For invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt
is generated. BDLC stops transmission.
CRC error interrupt is generated.
BDLC waits for EOF.
The BDLC aborts transmission immediately. Invalid symbol interrupt is generated.
Invalid symbol interrupt is generated. BDLC waits for end of frame (EOF).
The BDLC does not transmit until the bus is idle. Invalid symbol interrupt is generated.
EOF interrupt also must be seen before another transmission attempt. Depending on
length of the short, LOA flag also may be set.
Thermal overload shuts down physical interface. Fault condition is seen as invalid
symbol flag. EOF interrupt must also be seen before another transmission attempt.
Invalid symbol interrupt is generated. BDLC waits for the next valid SOF.
= Reserved
CLKS
M68HC12B Family Data Sheet, Rev. 9.1
6
1
R1
5
1
R0
4
0
BDLC Function
R
3
0
0
R
2
0
0
IE
1
0
WCM
Bit 0
0
BDLC Registers
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