MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 251

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16.6 Protocol Violation Protection
The msCAN12 will protect the user from accidentally violating the CAN protocol through programming
errors. The protection logic implements these features:
16.7 Low-Power Modes
In addition to normal mode, the msCAN12 has three modes with reduced power consumption compared
to normal mode. In sleep and soft-reset mode, power consumption is reduced by stopping all clocks
except those to access the registers. In power-down mode, all clocks are stopped and no power is
consumed.
The wait-for-interrupt (WAI) and STOP instructions put the MCU in low power-consumption standby
modes.
of modes is entered for the given settings of the bits CSWAI, SLPAK, and SFTRES. For all modes, an
msCAN wakeup interrupt can occur only if SLPAK = WUPIE = 1. While the CPU is in wait mode, the
msCAN12 can be operated in normal mode and emit interrupts. (Registers can be accessed via
background debug mode.)
Freescale Semiconductor
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•
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The receive and transmit error counters cannot be written or otherwise manipulated.
All registers which control the configuration of the msCAN12 cannot be modified while
the msCAN12 is online. The SFTRES bit in CMCR0 (see
Register
–
–
–
–
–
The TxCAN pin is forced to recessive if the CPU goes into stop mode.
Table 16-2
msCAN12 module control register 1 (CMCR1)
msCAN12 bus timing register 0 and 1 (CBTR0 and CBTR1)
msCAN12 identifier acceptance control register (CIDAC)
msCAN12 identifier acceptance registers (CIDAR0–CIDAR7)
msCAN12 identifier mask registers (CIDMR0–CIDMR7)
Wakeup
Error interrupts
Receive
Transmit
0) serves as a lock to protect these registers:
summarizes the combinations of msCAN12 and CPU modes. A particular combination
Function
Table 16-1. msCAN12 Interrupt Vectors
M68HC12B Family Data Sheet, Rev. 9.1
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
Source
WUPIF
OVRIF
TXE0
TXE1
TXE2
RXF
16.12.1 msCAN12 Module Control
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
TXEIE0
TXEIE1
TXEIE2
WUPIE
OVRIE
RXFIE
Local
Mask
Protocol Violation Protection
Global
Mask
I bit
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