MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 221

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

BDLC MUX Interface
When the last byte of a message has been transmitted onto the J1850 bus and the EOF symbol time has
expired, all nodes then must wait for the IFS symbol time to expire before transmitting a start-of-frame
(SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before beginning a transmission and a rising
edge is detected before the IFS time has expired, it synchronizes internally to that edge.
A rising edge may occur during the IFS period because of varying clock tolerances and loading of the
J1850 bus, causing different nodes to observe the completion of the IFS period at different times. To allow
for individual clock tolerances, receivers must synchronize to any SOF occurring during an IFS period.
15.7.2.8 BREAK — Break
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK as if a transmission error
had occurred and halts transmission.
If the BDLC detects a BREAK symbol while receiving a message, it treats the BREAK as a reception error
and sets the invalid symbol flag in the BSVR, also ignoring the frame it was receiving. If while receiving a
message in 4X mode, the BDLC detects a BREAK symbol, it treats the BREAK as a reception error, sets
the invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2 is cleared automatically).
If bus control is required after the BREAK symbol is received and the IFS time has elapsed, the
programmer must resend the transmission byte using highest priority.
15.7.2.9 IDLE — Idle Bus
An idle condition exists on the bus during any passive period after expiration of the IFS period (for
example, > 300 µs). Any node sensing an idle bus condition can begin transmission immediately.
15.7.3 J1850 VPW Symbols
Huntsinger’s variable pulse-width modulation (VPW) is an encoding technique in which each bit is defined
by the time between successive transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This encoding technique is used to reduce
the number of bus transitions for a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either the active or passive level and one
of two lengths, either 64 µs or 128 µs (t
at 10.4 Kbps baud rate), depending upon the encoding of the
NOM
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame (EOF), and inter-frame
separation (IFS) symbols are always encoded at an assigned level and length. See
Figure
15-5.
Each message begins with an SOF symbol, an active symbol, and, therefore, each data byte (including
the CRC byte) begins with a passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the descriptions here are typical values at a 10.4-Kbps bit rate. EOF, EOD,
IFS, and IDLE, however, are not driven J1850 bus states. They are passive bus periods observed by each
node’s CPU.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
221