MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 268

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

16.12.6 msCAN12 Receiver Interrupt Enable Register
WUPIE — Wakeup Interrupt Enable Bit
RWRNIE — Receiver Warning Interrupt Enable Bit
TWRNIE — Transmitter Warning Interrupt Enable Bit
RERRIE — Receiver Error Passive Interrupt Enable Bit
TERRIE — Transmitter Error Passive Interrupt Enable Bit
BOFFIE — Bus-Off Interrupt Enable Bit
OVRIE — Overrun Interrupt Enable Bit
RXFIE — Receiver Full Interrupt Enable Bit
268
msCAN12 Controller
0 = No interrupt is generated from this event.
1 = A wakeup event results in a wakeup interrupt.
0 = No interrupt is generated from this event.
1 = A receiver warning status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter warning status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receiver error passive status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter error passive status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A bus-off event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = An overrun event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receive buffer full (successful message reception) event results in a receive interrupt.
Address: $0105
The CRIER register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Reset:
Figure 16-21. msCAN12 Receiver Interrupt Enable Register (CRIER)
Read:
Write:
WUPIE
Bit 7
0
RWRNIE
6
0
M68HC12B Family Data Sheet, Rev. 9.1
TWRNIE
5
0
NOTE
RERRIE
4
0
TERRIE
3
0
BOFFIE
2
0
OVRIE
1
0
Freescale Semiconductor
RXFIE
Bit 0
0