MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 234

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Communications (BDLC)
RX4XE — Receive 4X Enable Bit
NBFS — Normalization Bit Format Select Bit
TEOD — Transmit End of Data Bit
TSIFR, TMIFR1, TMIFR0 — Transmit In-Frame Response Bits
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This bit determines if the BDLC operates at normal transmit and receive speed (10.4 Kbps) or receive
only at 41.6 Kbps. This feature is useful for fast downloading data into a J1850 node for diagnostic or
factory programming.
This bit controls the format of the normalization bit (NB). (See Figure 15-14.) SAE J1850 encourages
using an active long (logic 0) for in-frame responses containing cyclical redundancy check (CRC) and
an active short (logic 1) for in-frame responses without CRC.
This bit is set by the programmer to indicate the end of a message is being sent by the BDLC. It
appends an 8-bit CRC after completing transmission of the current byte. This bit also is used to end
an in-frame response (IFR). If the transmit shadow register is full when TEOD is set, the CRC byte is
transmitted after the current byte in the Tx shift register and the byte in the Tx shadow register have
been transmitted. (See
register.) Once TEOD is set, the transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur. (See
Register.)
These bits control the type of in-frame response being sent. Only one of these bits should be set at a
time. If more than one are set, the priority encoding logic forces the bits to a known value as shown in
Table
encoded as 010. However, when these bits are read back, they read 011.
1 = BDLC is put in 4X receive-only operation.
0 = BDLC transmits and receives at 10.4 Kbps. Reception of a BREAK symbol automatically clears
0 = NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR)
1 = NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR)
1 = Transmit end-of-data (EOD) symbol
0 = TEOD bit is cleared automatically at the rising edge of the first CRC bit that is sent or if an error
15-3. For example, if 011 is written to TSIFR, TMIFR1, and TMIFR0, then internally they are
this bit and sets BDLC state vector register (BSVR) to $001C.
ends with a CRC byte. NB that is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
ends with a CRC byte. NB that is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
is detected. When TEOD is used to end an IFR transmission, TEOD is cleared when the BDLC
receives back a valid EOD symbol or an error condition occurs.
1. Shaded cells indicate bits which do not affect internal interpretation. These bits read
TSIFR
back as written.
0
1
0
0
Table 15-3. Transmit In-Frame Response Bit Encoding
15.8.3 Rx and Tx Shadow Registers
Write/Read
TMIFR1
0
1
0
M68HC12B Family Data Sheet, Rev. 9.1
(1)
TMIFR0
0
1
TSIFR
0
1
0
0
Internal Interpretation
for a description of the transmit shadow
TMIFR1
0
0
1
0
15.9.3 BDLC State Vector
TMIFR0
0
0
0
1
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