MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 55

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
Addr.
$00FD
$00FE
$00FF
$0100
$0101
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$0104
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Notes:
↓
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
Port DLC Data Direction Register
msCAN12 Identifier Acceptance
msCAN12 Transmitter Control
msCAN12 Receiver Interrupt
Control Register (CIDAC)
Enable Register (CRIER)
msCAN12 Transmitter Flag
Register Name
Port DLC Control Register
msCAN12 Module Control
msCAN12 Module Control
msCAN12 Receiver Flag
Port DLC Data Register
Register 0 (CMCR0)
Register 1 (CMCR1)
msCAN12 Bus Timing
msCAN12 Bus Timing
Register 0 (CBTR0)
Register 1 (CBTR1)
Register (CRFLG)
Register (CTFLG)
Register (CTCR)
See page 241.
See page 242.
See page 242.
See page 262.
See page 263.
See page 264.
See page 265.
See page 266.
See page 268.
See page 269.
See page 270.
See page 270.
(PORTDLC)
(DDRDLC)
(DLCSCR)
Reserved
(2)
(2)
(2)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Figure 2-1. Register Map (Sheet 16 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
WUPIF
WUPIE
SAMP
SJW1
Bit 7
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
RWRNIF
RWRNIE
ABTRQ2
TSEG22
ABTAK2
DDDLC6
SJW0
Bit 6
U
R
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TWRNIE
ABTRQ1
TSEG21
TWRNIF
ABTAK1
DDDLC5
CSWAI
IDAM1
BRP5
Bit 5
U
R
5
0
0
0
1
0
0
0
0
0
0
0
0
0
ABTRQ0
TSEG20
RERRIE
ABTAK0
DDDLC4
RERRIF
SYNCH
IDAM0
BRP4
Bit 4
U
R
R
4
0
0
0
0
0
0
0
0
0
0
0
0
0
= Reserved
DDDLC3
TLNKEN
TSEG13
TERRIF
TERRIE
BPR3
Bit 3
U
R
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BDLCEN
DDDLC2
TSEG12
BOFFIE
LOOPB
BOFFIF
TXEIE2
SLPAK
IDHIT2
BPR2
TXE2
Bit 2
U
R
2
0
0
0
0
0
0
0
0
1
0
0
U = Unaffected
PUPDLC
DDDLC1
TSEG11
TXEIE1
SLPRQ
WUPM
OVRIE
IDHIT1
OVRIF
BPR1
TXE1
Bit 1
U
R
1
0
0
0
0
0
0
0
0
1
0
0
Registers
RDPDLC
CLKSRC
DDDLC0
SFTRES
TSEG10
TXEIE0
IDHIT0
RXFIE
BPR0
TXE0
Bit 0
Bit 0
RXF
U
R
0
0
1
0
0
0
0
0
1
0
0
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