MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 229

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Once the Tx shift register has completed its shifting operation for the current byte, the data byte in the Tx
shadow register is loaded into the Tx shift register. After this transfer takes place, the Tx shadow register
is ready to accept new data from the CPU when the TDRE flag in the BSVR is set.
15.8.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or BDRxD, depending on the state of the
DLOOP bit in the BCR2. (See
15.8.5 State Machine
All functions associated with performing the protocol are executed or controlled by the state machine. The
state machine is responsible for framing, collision detection, arbitration, CRC generation/checking, and
error detection. These sections describe the BDLC’s actions in a variety of situations.
15.8.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a special 4X (41.6 Kbps) mode of
J1850 variable pulse width modulation (VPW) operation. The BDLC cannot transmit in 4X mode, but it
can receive messages in 4X mode, if the RX4X bit is set in BCR2. If the RX4X bit is not set in the BCR2,
any 4X message on the J1850 bus is treated as noise by the BDLC and is ignored.
15.8.5.2 Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC does allow for a special block mode of operation
of the receiver. As far as the BDLC is concerned, a block mode message is simply a long J1850 frame
Freescale Semiconductor
DLOOP FROM BCR2
LOOPBACK CONTROL
Figure 15-11. BDLC Protocol Handler Outline
15.9.2 BDLC Control Register
M68HC12B Family Data Sheet, Rev. 9.1
Rx SHADOW REGISTER
Rx SHIFT REGISTER
BDRxD
MULTIPLEXER
LOOPBACK
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
TO PHYSICAL INTERFACE
STATE MACHINE
BDTxD
2.)
Tx SHADOW REGISTER
Tx SHIFT REGISTER
8
BDLC Protocol Handler
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