MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 223

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.7.3.5 Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by an active period 200 µs in length
(see
regardless of whether it is a logic 1 or a logic 0.
15.7.3.6 End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 µs in
length (see
15.7.3.7 End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed by a passive period 280 µs in
length (see
µs the EOD becomes an EOF, indicating completion of the message.
15.7.3.8 Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The 20-µs IFS symbol contains no
transition, since when it is used it always appends to a 280-µs EOF symbol (see
15.7.3.9 Idle
An idle is defined as a passive period greater than 300 µs in length.
15.7.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow
for variations in oscillator frequencies. In many cases, the maximum time allowed to define a data bit or
symbol is equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being received is equal to a
single period of the MUX interface clock (t
time concurrences equals one cycle of t
This one clock resolution allows the BDLC to differentiate properly between the different bits and symbols.
This is done without reducing the valid window for receiving bits and symbols from transmitters onto the
J1850 bus, which has varying oscillator frequencies.
In Huntsinger’s variable pulse width (VPW) modulation bit encoding, the tolerances for both the passive
and active data bits received and the symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1,
and the maximum length of an active logic 0 is equal to the minimum length of a valid SOF symbol.
See
Freescale Semiconductor
Figure
Figure
15-6,
Figure
Figure
15-5(D)). This allows the data bytes which follow the SOF symbol to begin with a passive bit,
Figure
15-5(F)). If no IFR byte is transmitted after an EOD symbol is transmitted, another 80
15-5(E)).
15-7, and
Figure
M68HC12B Family Data Sheet, Rev. 9.1
BDLC
BDLC
15-8.
.
), an apparent separation in these maximum time/minimum
Figure
BDLC MUX Interface
15-5(G)).
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