MC68HC912B32CFU8 Freescale Semiconductor, MC68HC912B32CFU8 Datasheet - Page 145

• Manufacturer Part Number: MC68HC912B32CFU8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC68HC912B32CFU8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TSBCK — Timer Stops While in Background Mode Bit
TFFCA — Timer Fast Flag Clear All Bit
12.3.6 Timer Control Registers
Read: Anytime
Write: Anytime
OMn — Output mode
OLn — Output level
Freescale Semiconductor
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare (see
becomes an output tied to OCn regardless of the state of the associated DDRT bit.
0 = Allows timer to continue running while in background mode
1 = Disables timer when MCU is in background mode; useful for emulation
0 = Allows timer flag clearing to function normally
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel
($90–$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any
access to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register
($A2 and $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1).
This has the advantage of eliminating software overhead in a separate clear sequence.
Address: $0088
Address: $0089
Extra care is required to avoid accidental flag clearing due to unintended
accesses.
Reset:
Reset:
Read:
Read:
Write:
Write:
OMn
0
0
1
1
OM7
OM3
Bit 7
Bit 7
0
0
Figure 12-8. Timer Control Register 1 (TCTL1)
Figure 12-9. Timer Control Register 2 (TCTL2)
Table 12-1. Compare Result Output Action
OL7
OL3
Table
OLn
6
0
6
0
0
1
0
1
M68HC12B Family Data Sheet, Rev. 9.1
12-1). When either OMn or OLn is 1, the pin associated with OCn
OM6
OM2
5
0
5
0
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to 0
Set OCn output line to 1
NOTE
OL6
OL2
4
0
4
0
OM5
OM1
3
0
3
0
Action
OL5
OL1
2
0
2
0
OM4
OM0
1
0
1
0
Bit 0
Bit 0
OL4
OL0
0
0
Block Diagram
145