XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 11

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
T
F
S
S
F
S
E
R
S
S
R
S
FIFO L
R
R
R
R
F
S
F
S
S
E
F
HIRD
IFTH
OURTH
IRST
IFTH
IRST
EVENTH
ECOND
IXTH
IGHTH
LIP
LIP
LIP
ECOND
IXTH
EVENTH
IGHTH
6.2 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK................................................................. 275
ECEIVE
ECEIVE
ECEIVE
ECEIVE
ECEIVE
ECEIVE
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
B
B
B
6.2.1 DESCRIPTION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK............................................. 275
6.2.2 BRIEF DISCUSSION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK OPERATING AT XRT84V24
6.2.3 HIGH SPEED RECEIVE BACK-PLANE INTERFACE................................................................................................ 286
O
O
O
O
O
O
O
UFFER
UFFER
UFFER
ATENCY
CTET OF
O
CTET OF
O
CTET OF
CTET OF
CTET OF
CTET OF
CTET OF
O
O
O
I
I
I
M
M
I
82. W
O
CTET OF
79. I
80. T
NTERFACE
NTERFACE
81. I
83. I
84. W
85. I
86. W
NTERFACE
NTERFACE
87. I
88. T
89. I
90. T
91. I
92. T
O
CTET OF
93. I
94. T
COMPATIBLE 2.048MBIT/S MODE ............................................................................................................................ 276
6.2.2.1 C
6.2.2.2 C
6.2.2.3 C
6.2.3.1 E1 R
6.2.3.2 E1 R
6.2.3.3 E1 R
6.2.3.4 E1 R
6.2.3.5 E1 R
CTET OF
CTET OF
CTET OF
ULTIPLEX
ULTIPLEX
CTET OF
CTET OF
AS RECEIVE TIMING SOURCE
E
S
NAL
NAL
QUIPMENT WHEN THE
ECTION
NTERFACING
NTERFACING
NTERFACING
NTERFACING
NTERFACING
NTERFACING
NTERFACING
NTERFACING
C
C
S
IMING SIGNAL WHEN THE FRAMER IS RUNNING AT
IMING
IMING
IMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT
IMING SIGNAL WHEN THE FRAMER IS RUNNING AT
B
B
B
AVEFORMS OF THE
AVEFORMS OF THE
AVEFORMS OF THE
TATUS
ONTROL
ONTROL
E
E
R
UFFER IS BYPASSED
UFFER IS ENABLED
UFFER IS CONFIGURED AS
QUIPMENT WHEN THE
QUIPMENT WHEN THE
16.384M
16.384M
16.384M
16.384M
16.384M
16.384M
EGISTER
16.384M
ONNECT THE
ONNECT THE
ONNECT THE
16.384M
16.384M
D
D
..................................................................................................................................................................... 281
16.384M
16.384M
16.384M
IAGRAM OF
IAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT
16.384M
C
C
C
C
ECEIVE
ECEIVE
ECEIVE
ECEIVE
16.384M
ECEIVE
E
E
R
ONTROL
ONTROL
ONTROL
NABLE
NABLE
ONTROL
XRT84L38
EGISTER
XRT84L38
R
R
XRT84L38
XRT84L38
XRT84L38
XRT84L38
XRT84L38
XRT84L38
EGISTER
EGISTER
BIT
BIT
BIT
BIT
BIT
(FIFOL) (I
BIT
BIT
I
I
I
I
I
NPUT
NPUT
NPUT
NPUT
NPUT
BIT
BIT
R
R
R
BIT
BIT
BIT
/
/
/
B
B
/
/
/
S
/
I
S
BIT
ECEIVE
ECEIVE
ECEIVE
S
BIT
S
S
S
S
S
NPUT SIGNALS TO THE
S
S
S
IGNALS
............................................................................................................................................... 281
IT
IT
/
/
R
R
IGNALS THAT
IGNALS THAT
R
R
/
S
LIP
S
D
/
D
/
D
D
D
............................................................................................................................................. 279
I
I
I
I
D
I
D
S
S
NTERFACE
NTERFACE
NTERFACE
NTERFACE
S
NTERFACE
/
EGISTER
EGISTER
(SBSR) (I
EGISTER
EGISTER
/
= 0 ........................................................................................................ 287
= 1 ........................................................................................................ 288
TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER BYPASSED AND RECOVERED RECEIVE LINE CLOCK
ATA
S
TO LOCAL TERMINAL EQUIPMENT USING
TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER ENABLED OR ACTS AS FIFO
TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER ENABLED OR ACTS AS FIFO
TO LOCAL TERMINAL EQUIPMENT USING
TO LOCAL TERMINAL EQUIPMENT USING
TO LOCAL TERMINAL EQUIPMENT USING
ATA
S
TO LOCAL TERMINAL EQUIPMENT USING
D
ATA
D
ATA
ATA
ATA
ATA
S
S
......................................................................................................................................... 280
D
D
B
D
(SBCR) (I
(SBCR) (I
ATA
LIP
LIP
ATA
D
D
UFFER IS
P
P
P
ATA
ATA
ATA
FIFO ........................................................................................................................... 284
C
ATA
AYLOAD
AYLOAD
AYLOAD
ATA
NDIRECT
S
S
S
S
S
B
B
S
ONNECTING THE
S
UFFER IS
UFFER IS ACTED AS
TREAM
TREAM
TREAM
TREAM
TREAM
S
TREAM
S
TREAM
S
S
S
TREAM
TREAM
S
- MVIP 2.048 MH
- 4.096 MH
- 8.192 MH
- B
S
- HMVIP 16.384M
C
C
(RICR) (I
(RICR) (I
(RICR) (I
(RICR) (I
TREAM
TREAM
TREAM
NDIRECT
TREAM
ONNECT THE
ONNECT THE
TREAM
B
IT
D
D
D
YPASSED AND THE
NDIRECT
NDIRECT
-M
ATA
ATA
ATA
.......................................................................................... 272
.......................................................................................... 293
.......................................................................................... 294
.......................................................................................... 296
A
......................................................................................... 272
......................................................................................... 273
E
......................................................................................... 294
ULTIPLEXED
NABLED
F
....................................................................................... 273
DDRESS
....................................................................................... 294
...................................................................................... 273
...................................................................................... 273
...................................................................................... 293
O
O
O
RAMER WHEN RUNNING AT
.................................................................................... 273
.................................................................................... 294
UTPUT
UTPUT
UTPUT
Z
Z
R
NDIRECT
NDIRECT
NDIRECT
A
NDIRECT
....................................................................................................... 290
....................................................................................................... 291
ECEIVE
H.100 16.384M
B
R
R
DDRESS
VII
A
A
................................................................................................... 284
IT
ECEIVE
ECEIVE
FIFO......................................................................................... 286
DDRESS
DDRESS
-M
Z
I
I
I
BIT
NTERFACE BLOCK TO THE
NTERFACE BLOCK TO THE
NTERFACE BLOCK TO THE
= 0
............................................................................................. 288
16.384M
ULTIPLEXED
P
/
S
R
AYLOAD
XN
A
....................................................................................... 295
A
A
ECOVERED
P
P
A
DDRESS
= 0
AYLOAD
AYLOAD
DDRESS
DDRESS
DDRESS
0H, 0
= 0
= 0
16.384M
MVIP 2.048M
4.096M
8.192M
BIT
16.384 M
XN
BIT
D
/
XN
XN
16.384M
ATA
S
AH, 0
/
X
S MODE
D
D
....................................................................... 292
17H) .............................................. 284
8.192M
0H, 0
0H, 0
L
ATA
ATA
4.096M
MVIP 2.048M
= 0
INE
BIT
BIT
= 0
= 0
O
= 0
BIT
UTPUT
BIT
/
/
O
O
XN
S DATA BUS
S DATA BUS
C
X
/
XN
XN
XN
BIT
S DATA BUS
/
........................................................... 275
UTPUT
UTPUT
08H)...................................... 282
LOCK IS THE
S DATA BUS
X
X
BIT
BIT
0H, 0
BIT
16H) ................................... 276
16H) ................................... 277
0H, 0
0H, 0
0H, 0
/
L
L
L
S MODE
I
/
/
OCAL
NTERFACE BLOCK TO THE LOCAL
OCAL
OCAL
/
S DATA BUS
S MODE
S MODE
I
I
NTERFACE BLOCK TO THE LOCAL
NTERFACE BLOCK TO THE LOCAL
BIT
X
OCTAL T1/E1/J1 FRAMER
X
X
X
22H) ......................... 288
T
T
T
........................................... 290
........................................... 292
22H) ........................ 276
22H) ........................ 278
22H) ........................ 286
.......................................... 295
/
......................................... 274
ERMINAL
ERMINAL
ERMINAL
S
........................................ 292
........................................ 295
T
....................................... 291
...................................... 289
IMING
.................................. 289
S
E
E
E
OURCE OF THE
QUIPMENT IF THE
QUIPMENT IF THE
QUIPMENT IF THE
..................... 283
..................... 285
XRT84L38
T
R
ERMINAL
ECEIVE
T
T
S
S
S
ERMI
ERMI
LIP
LIP
LIP
-
-