XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 234

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Each of the eight framers within the XRT84L38 includes a Receive Payload Data Output Interface block. The
function of the block is to provide an interface to the Terminal Equipment (for example, a Central Office or
switching equipment) that has data to receive from a "Far End" terminal over a DS1 or E1 transport medium.
The Payload Data Output Interface module (also known as the Back-plane Interface module) supports payload
data to be taken from or presented to the system. In DS1 mode, supported data rates are 1.544Mbit/s, MVIP
2.048Mbit/s, 4.096Mbit/s, 8.192Mbit/s, multiplexed 12.352Mbit/s, multiplexed 16.384Mbit/s, HMVIP
16.384Mbit/s or H.100 16.384Mbit/s. In E1 mode, supported data rates are XRT84V24 compatible 2.048Mbit/s,
MVIP 2.048Mbit/s, 4.096Mbit/s, 8.192Mbit/s, multiplexed 16.384Mbit/s, HMVIP 16.384Mbit/s or H.100
16.384Mbit/s.
The Receive Payload Data Output Interface block supplies or accepts the following signals to the Terminal
Equipment circuitry:
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•
•
•
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The Receive Serial Data is an output pin carrying payload, signaling and sometimes Data Link data supplied by
XRT84L38 to the local Terminal Equipment.
The Receive Serial Clock is an input or output signal used by the Receive Payload Data Input Interface block
to send out serial data to the local Terminal Equipment. The Receive Clock Inversion bit of the Receive
Interface Control Register (TICR) determines at which edge of the Receive Serial Clock would data transition
on the Receive Serial Data pin occur.
The table below shows configurations of the Receive Clock Inversion bit of the Receive Interface Control
Register (RICR).
RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0xn0H, 0x22H)
Throughout the discussion of this datasheet, we assume that serial data transition happens on the rising edge
of the Receive Serial Clock unless stated otherwise.
The Receive Single-frame Synchronization signal is either input or output. When configured as input, it
indicates beginning of a DS1 frame. When configured as output, it indicates the end of a DS1 frame.
The Receive Multi-frame Synchronization signal is an output pin from XRT84L38 indicating the end of a DS1
multi-frame.
By connecting these signals with the local Terminal Equipment, the Receive Payload Data Output Interface
routes received payload data from the Receive Framer Module to the local Terminal Equipment.
5.0 THE DS1 RECEIVE SECTION
5.1
5.1.1
5.1.2
N
Receive Serial Data Input (RxSer_n)
Receive Serial Clock (RxSerClk_n)
Receive Single-frame Synchronization Signal (RxSync_n)
Receive Multi-frame Synchronization Signal (RxMSync_n)
Receive Time-slot Indicator Clock (RxTSClk_n)
Receive Time-slot Indication Bits (RxTSb[4:0]_n)
UMBER
B
3
IT
The DS1 Receive Payload Data Output Interface Block
Description of the Receive Payload Data Output Interface Block
The Receive Payload Data Output Interface Block Operating at 1.544Mbit/s mode
Receive Clock
B
Inversion
IT
N
AME
B
IT
R/W
T
YPE
0 - Serial data transition happens on rising edge of the Receive Serial Clock.
1 - Serial data transition happens on falling edge of the Receive Serial Clock.
214
B
IT
D
ESCRIPTION
REV. 1.0.1