XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 249
XRT84L38IB
Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet
1.XRT84L38.pdf
(453 pages)
Specifications of XRT84L38IB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REV. 1.0.1
See
Interface block of the framer in MVIP 2.048Mbit/s mode.
The timing diagram of input signals to the framer when running at MVIP 2.048Mbit/s mode is shown in
Figure
This interface mode is the same as running at 2.048 MHz. The only difference is that the Receive Serial Clock
runs two times faster at 4.096 MHz.
F
F
5.1.3.2
IGURE
IGURE
RxTSb[2]/RxChn
(RxSyncFrTD=1)
(RxSyncFrTD=1)
Figure 49
RxTSb[1]/FrRxD
RxTSb[0]/RxSig
RxSerClk(INV)
RxSync(input)
RxSync(input)
RxTSClk(INV)
50.
49. I
50. T
RxSerClk
RxTSClk
RxTSClk
(MVIP)
RxSer
NTERFACING
IMING
T1 Receive Input Interface - 4.096 MHz
below for how to interface the local Terminal Equipment with the Receive Payload Data Output
F
D
IAGRAM OF
Equipment
XRT84L38
Terminal
I
NPUT SIGNALS TO THE
c1 c2 c3 c4 c5
1
2
Timeslot 1
TO LOCAL
3
4
A B
5
6
RxSerClk_0 (2.048MHz)
RxSer_0
RxMSync_0
RxSync_0
RxSerClk_7 (2.048MHz)
RxSer_7
RxMSync
RxSync_7
C
7
D
8
T
c1 c2 c3 c4 c5
1
ERMINAL
1
2
2
Timeslot 2
3
3
229
4
4
F
[
A B
5
5
RAMER WHEN RUNNING AT
E
6
6
QUIPMENT USING
7
C
7
D
8
8
c1 c2 c3 c4 c5
1
2
Timeslot 3
3
4
A B
5
Data Input
Data Input
Interface
Interface
Receive
Payload
Receive
Payload
6
Chn 0
Chn 7
C
7
XRT84L38
MVIP 2.048M
D
8
OCTAL T1/E1/J1 FRAMER
MVIP 2.048M
BIT
1
/
c1 c2 c3 c4 c5
1
S
2
2
D
XRT84L38
BIT
Timeslot 4
3
3
ATA
4
4
/
S
5
5
A B
B
6
6
US
7
C
7
8
D
8
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