XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 356

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XRT84L38IB

Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT84L38IB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
XRT84L38
OCTAL T1/E1/J1 FRAMER
10.3
The XRT84L38 T1/J1/E1 Octal Framer provides individual control of each of the twenty-four DS0 channels.
The user can apply data and signaling conditioning to the received DS1 payload data coming from the DS1 LIU
Receive Block on a per-channel basis.
The XRT84L38 framer can apply the following changes to the received DS1 payload data coming from the
Terminal Equipment on a per-channel basis:
Configurations of the XRT84L38 framer to apply the above-mentioned changes to the received DS1 PAYLOAD
data are controlled by the Receive Data Conditioning Select [3:0] bits of the Receive Channel Control Register
(RCCR) of each DS0 channel.
The XRT84L38 framer can also replace the incoming DS1 payload data from the DS1 LIU Receive Block with
pre-defined or user-defined codes. The XRT84L38 supports the following conditioning substitutions:
Once again, configuration of the XRT84L38 framer to replace the received DS1 payload data with the above-
mentioned coding schemes are controlled by the Receive Data Conditioning Select [3:0] bits of the Receive
Channel Control Register (RCCR) of each DS0 channel.
Finally, the XRT84L38 framer can configure any one or ones of the twenty-four DS0 channels to be D or E
channels. D channel is used primarily for data link applications. E channel is used primarily for signaling for
circuit switching with multiple access configurations.
The Receive Data Conditioning Select [3:0] bits of the Receive Channel Control Register (RCCR) of each
channel determine whether that particular channel is configured as D or E channel.
All 8 bits of the received payload data are inverted
The even bits of the received payload data are inverted
The odd bits of the received payload data are inverted
The MSB of the received payload data is inverted
All received payload data except the MSB are inverted
BUSY code - an octet with hexadecimal value of 0x7F
BUSY_TS code - an octet of pattern "111xxxxx" where "xxxxx" represents the timeslot number
VACANT code - an octet with hexadecimal value of 0xFF
A-law Digital Milliwatt code
u-law Digital Milliwatt code
IDLE code - an octet defined by the value stored in the User IDLE Code Register (UCR)
MOOF code - MUX-Out-Of-Frame code with hexadecimal value of 0x1A
PRBS code - an octet generated by the Pseudo-Random Bit Sequence (PRBS) Generator block of the
framer
How to Configure the Framer to Apply Data and Signaling Conditioning to Received DS1
Payload Data on a Per-Channel Basis
336
REV. 1.0.1

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