XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 240

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Equipment when the Slip Buffer is bypassed and the Recovered Receive Line Clock is timing source of the
Receive section.
By setting the Slip Buffer Enable [1:0] bits of the Slip Buffer Control Register to 01, the framer includes the two-
frame Elastic Buffer into its data path. The Receive Framer Module routes the Receive Payload Data to the
Elastic Buffer first. The Receive Payload Data is then presented to the Receive Payload Data Output Interface.
The XRT84L38 uses the Recovered Receive Line Clock internally to clock in the Receive Payload Data into
the Elastic Buffer. The Terminal Equipment should provide a 1.544MHz clock to the Receive Serial Clock input
pin to latch data out from the Elastic Buffer.
The Recovered Receive Line Clock and the Receive Serial Clock are generated from two different timing
sources. That is, the Recovered Receive Line Clock is originating from a remote site while Receive Serial
Clock generating by a local oscillator. Any mismatch in frequencies of these two clocks will result in the Slip
Buffer to gradually fill or deplete.
Overtime, the Elastic Buffer either fills or empties completely. Once that happened, a controlled slip by the
XRT84L38 will occur. The Receive Slip Buffer Slip bit of the Slip Buffer Status Register (SBSR) is set to 1.
If the buffer empties and a read occurs, then a full frame of data will be repeated and the Receive Slip Buffer
Empty bit of the Slip Buffer Status Register (SBSR) will be forced HIGH. If the buffer fills and a write comes,
then a full frame of data will be deleted and the Receive Slip Buffer Full bit of the Slip Buffer Status Register
(SBSR) will be forced HIGH.
The following table demonstrates settings of the Receive Slip Buffer Slip bit, Receive Slip Buffer Empty bit and
Receive Slip Buffer Full bit of the Slip Buffer Status Register.
F
TO THE LOCAL
THE
5.1.2.2
IGURE
RxTSb[1]/RxFrTD
T
RxTSb[2]/RxTSb
RxTSb[0]/RxSig
RxSync(output)
IMING
RxSync(input)
44. W
RxTSb[4:0]
RxSerClk
RxTSClk
RxTSClk
S
OURCE OF THE
RxSer
Connect the Receive Payload Data Output Interface block to the Local Terminal
Equipment if the Slip Buffer is enabled
AVEFORMS OF THE
T
ERMINAL
E
c1 c2 c3 c4 c5
QUIPMENT WHEN THE
R
Timeslot #0
Timeslot 0
ECEIVE
S
A B
IGNALS
S
C
ECTION
D
C
ONNECTING THE
S
LIP
c1 c2 c3 c4 c5
B
Timeslot #5
Timeslot 5
220
UFFER IS
A B
R
ECEIVE
C
B
D
YPASSED AND THE
c1 c2 c3 c4 c5
1
2
P
Timeslot #6
Timeslot 6
Input Data
AYLOAD
3
4
A B
5
6
D
C
7
ATA
D
8
R
O
ECOVERED
UTPUT
c1 c2 c3 c4 c5
I
Timeslot #16
NTERFACE BLOCK
Timeslot 16
Input Data
L
INE
A B
C
REV. 1.0.1
LOCK IS
C
D