XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 31

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
TRANSMIT SERIAL DATA INPUT
(Framer Channel Number indicated by _n)
S
IGNAL
TxTSb0_0
TxTSb0_1
TxTSb0_2
TxTSb0_3
TxTSb0_4
TxTSb0_5
TxTSb0_6
TxTSb0_7
TxTSb1_0
TxTSb1_1
TxTSb1_2
TxTSb1_3
TxTSb1_4
TxTSb1_5
TxTSb1_6
TxTSb1_7
TxInClk_0
TxInClk_1
TxInClk_2
TxInClk_3
TxInClk_4
TxInClk_5
TxInClk_6
TxInClk_7
TxFrTD_0
TxFrTD_1
TxFrTD_2
TxFrTD_3
TxFrTD_4
TxFrTD_5
TxFrTD_6
TxFrTD_7
TxSig_0
TxSig_1
TxSig_2
TxSig_3
TxSig_4
TxSig_5
TxSig_6
TxSig_7
N
AME
AC26
AC13
AC13
AC24
AC24
AF21
AF10
AB24
AF20
AB24
AF20
AF19
AF12
AF19
AF12
P
AE6
D15
G24
AC7
D15
G24
AC7
C22
H23
AD6
C22
H23
AD6
B13
A22
F26
A23
A23
B15
B15
C6
C8
C8
D9
D9
IN
#
T
YPE
O
O
I
I
I
Transmit Input Clock Signal -- Transmit Framer _n (continued)
Transmit Back-plane Interface-H.100, 16.384 MHz Clock Mode
If TxMUXEN = 1 and TxIMODE[1:0] = 11 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking multiplexed data at a rate
of 16.384 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals
running at 16.384 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not
required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and
latched into Transmit back-plane interface using clock edge of TxInClk_0 via
TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-
plexed and latched into Transmit back-plane interface using clock edge of
TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-
plexed into 8 channels from the serial inputs of Channel 0 and 4.
Transmit Framer_n--Time Slot Octet Identifier Output-Bit [0:4]:
These output signals (TxTSb4_n through TxTSb0_n) reflects the five-bit binary
value of the number of Time Slot (in the incoming DS1 frame), being accepted
and processed by the Transmit Payload Data Input Interface block associated
with Framer_n.
Terminal Equipment should use the TxTSClk_n clock signal to sample the five
output pins of each channel in order to identify the time-slot being processed
by the Transmit Payload Data Input Interface block of Framer_n.
Transmit Serial Signaling Input--Transmit Framer_n
These pins can be used to input robbed-bit signaling data within an outbound
DS1 frame or to input Channel Associated Signaling (CAS) bits within an out-
bound E1 frame, if Framer_n is configured accordingly.
Transmit Framer_n--Time Slot Octet Identifier Output-Bit 1:
These output signals (TxTSb4_n through TxTSb0_n) reflects the five-bit binary
value of the number of Time Slot (in the incoming DS1 frame), being accepted
and processed by the Transmit Payload Data Input Interface block associated
with Framer_n.
Terminal Equipment should use the TxTSClk_n clock signal to sample the five
output pins of each channel in order to identify the time-slot being processed
by the Transmit Payload Data Input Interface block of Framer_n.
Transmit Serial Fractional T1/E1 Input--Transmit Framer_n
bound DS1/E1 frame, if Framer_n is configured accordingly. In this mode, ter-
minal equipment will use either TxTSClk_n or TxSerClk_n output pins to clock
out fractional DS1/E1 payload data. Framer_n will then use TxTSClk_n or
TxSerClk_n to clock in fractional DS1/E1 payload data. Please see pin
description of TxTSClk_n for details.
These pins can be used to input fractional DS1/E1 payload data within an out-
11
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38