XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 333
XRT84L38IB
Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet
1.XRT84L38.pdf
(453 pages)
Specifications of XRT84L38IB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REV. 1.0.1
•
•
Figure 108
Overhead Input Interface module in E1 framing format mode.
The E1 Receive Overhead Output Interface Block will allow an external device to be the consumer of the E1
National bit sequence. This interface provides interface signals and required interface timing to shift out proper
data link information at proper time.
The Receive Overhead Output Interface for a given Framer consists of two signals.
•
•
The Receive Overhead Output Interface Clock Output pin (RxOHCLK_n) generates a rising clock edge for
each National bit that is configured to carry Data Link information according to setting of the framer. The data
link bits extracted from the incoming E1 frames are outputted from the Receive Overhead Output Interface
Output pin (RxOH_n) before the rising edge of RxOHClk_n. The Data Link equipment should sample and latch
the data link bits at the rising edge of RxOHClk_n.
F
8.2
8.2.1
IGURE
The Data Link equipment interfaced to the Transmit Overhead Input Interface should update the data on the
TxOH_n line upon detection of the rising edge of TxOHClk_n.
The Transmit Overhead Input Interface will sample and latch the data on the TxOH_n line on the falling edge
of TxOHClk_n.
RxOHClk_n: The Receive Overhead Output Interface Clock Output signal
RxOH_n: The Receive Overhead Output Interface Output signal.
TxMSync(output)
108. E1 T
TxMSync(input)
E1 Receive Overhead Interface
TxSync(output)
TxSync(input)
Description of the E1 Receive Overhead Output Interface Block
below shows the timing diagram of the input and output signals associated with the E1 Transmit
TxSync(out)
TxSync(in)
TxOhClk
TxSerClk
Frame #
TxOhClk
RANSMIT
TxSer
TxOh
TxOh
O
VERHEAD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LSB
I
NPUT
Si
I
NTERFACE
1
A
Timeslot 0
Sa4
Sa4
313
T
Sa5
IMING
Sa6
Sa7
Sa7
Sa8
Sa8
MSB
OCTAL T1/E1/J1 FRAMER
Timeslot 1
XRT84L38
LSB
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