XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 421

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
A transmitting data link layer entity shall examine the frame content between the opening and closing flag
sequences, (address, control, information and FCS field) and shall insert a 0 bit after all sequences of five
contiguous 1 bits (including the last five bits of the FCS) to ensure that an IDLE flag or an Abort sequence is
not simulated within the frame. A receiving data link layer entity shall examine the frame contents between the
opening and closing flag sequences and shall discard any 0 bit which directly follows five contiguous 1 bits.
13.1.4.2
This section describes how to configure the LAPD Controller Block to transmit MOS message in a step-by-step
basis.
13.1.4.2.1
To transmit MOS message, the user is recommended to read Transmit Data Link Byte Count Register for next
available transmit buffer number.
The table below shows how contents of the Buffer Enable bit of the Transmit Data Link Byte Count Register
(TDLBCR) determines what the next available transmit buffer number is.
TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X14H)
13.1.4.2.2
After finding out the next available transmit buffer, the user should write the entire message data to the
available transmit data link buffer via PIO or DMA access. The writing of these buffers is through the LAPD
Buffer 0 indirect data registers and the LAPD Buffer1 indirect data registers. LAPD Buffer 0 and 1 indirect data
registers have addresses 0xn6H and 0xn7H respectively. There is no indirect address register for transmit data
link buffer 0 and 1.
A microcontroller WRITE access to the LAPD Buffer indirect data registers will access the transmit data link
buffer and a microcontroller READ will access the receive data link buffers. The very first WRITE access to the
LAPD Buffer indirect data register will always be direct to location 0 within the transmit data link buffer. The
next WRITE access to the LAPD Buffer indirect data register will be direct to location 1 within the transmit data
link buffer and so on, until all 96 bytes of the transmit buffer is filled.
For example, if the first byte of the MOS message to be sent is (01010110) and the next available transmit data
link buffer of Channel n is 1. The user should write pattern (01010110) into transmit data link buffer 1 of
Channel n. The following microprocessor access to the framer should be done:
WR
The first byte of MOS message is written into location 0 of the transmit data link buffer. If the next byte of the
MOS message is (10100101), the user should perform another microprocessor WRITE access:
WR
The second byte of MOS message is written into location 1 of the transmit data link buffer. The WRITE access
should be repeated until the entire block of MOS message is written into the transmit buffer or the transmit
buffer is completely filled.
13.1.4.2.3
The user should program byte count of the MOS message into the Transmit Data Link Byte Count Register
after the whole block of data is present in the buffer memory.
N
UMBER
B
7
IT
n7H
n7H
How to configure the Transmit HDLC Controller Block to transmit MOS
Buffer Select
Step 1: Find out the next available transmit data link buffer
Step 2: Write MOS Message into transmit data link buffer
Step 3: Program the Transmit Data Link Byte Count Register
B
56H
A5H
IT
N
AME
B
IT
R
T
YPE
0 - The next available transmit buffer for sending out BOS or MOS mes-
sage is Buffer 0.
1 - The next available transmit buffer for sending out BOS or MOS mes-
sage is Buffer 1.
401
B
IT
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38