XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 237

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The Receive Time-slot Indication Bits (RxTSb[4:0]_n) are multiplexed I/O pins. The functionality of these pins
is governed by the value of Receive Fractional T1 Output Enable bit of the Receive Interface Control Register
(RICR). The following table illustrates the configurations of the Receive Fractional DS1 Input Enable bit.
RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0xn0H, 0x22H)
When configured to operate in normal condition (that is, when the Receive Fractional T1 Input Enable bit is
equal to zero), these bits reflect the five-bit binary value of the Time Slot number (0 - 23) being outputted and
processed by the Receive Payload Data Output Interface block of the framer. RxTSb[4] represents the MSB of
the binary value and RxTSb[0] represents the LSB.
When the Receive Fractional T1 Output Enable bit is equal to one, the RxTSb[0]_n bit becomes the Receive
Fractional T1 Output signal (RxFrTD_n). This output pin carries Fractional T1 Output data extracted by the
framer from the incoming DS1 data stream. The Fractional T1 Output Interface allows certain time-slots of DS1
data to be routed to destinations other than the local Terminal Equipment. Function of the Fractional T1 Output
signal will be discussed in details in later sections.
When the Receive Fractional T1 Output Enable bit is equal to one, the RxTSb[1]_n bit becomes the Receive
Signaling Data Output signal (RxSig_n). These output pins can be used to carry robbed-bit signaling data
extracted from the inbound DS1 frame. Function of the Receive Signaling Data Output signal will be discussed
in details in later sections.
When the Receive Fractional T1 Output Enable bit is equal to one, the RxTSb[2]_n bit serially outputs all five-
bit binary values of the Time Slot number (0-23) being outputted and processed by the Receive Payload Data
Output Interface block of the framer. MSB of the binary value is presented first and the LSB is presented last.
The RxTSb[3]_n and RxTSb[4}_n pins are not multiplexed.
N
UMBER
B
4
IT
Fractional DS1
Output Enable
B
Receive
IT
N
AME
B
IT
R/W
T
YPE
0 - The Receive Time-slot Indication bits (RxTSb[4:0] are outputting five-bit
binary values of Time-slot number (0-23) being accepted and processed by the
Receive Payload Data Output Interface block of the framer.
The Receive Time-slot Indicator Clock signal (RxTSClk_n) is a 192KHz clock
that pulses HIGH for one DS1 bit period whenever the Receive Payload Data
Output Interface block is accepting the LSB of each of the twenty-four time slots.
1 - The RxTSb[0]_n bit becomes the Receive Fractional T1 Output signal
(RxFrTD_n) which carries Fractional DS1 payload data from the framer.
The RxTSb[1]_n bit becomes the Receive Signaling Data Output signal
(RxSig_n) which is used to carry robbed-bit signaling data extracted from the
inbound DS1 frame.
The RxTSb[2]_n bit serially outputs all five-bit binary values of the Time Slot
number (0-23) being accepted and processed by the Receive Payload Data Out-
put Interface block of the framer.
The RxTSClk_n will output gaped fractional DS1 clock that can be used by Ter-
minal Equipment to latch in Fractional DS1 payload data at rising edge of the
clock. Or,
The RxTSClk_n pin will be a clock enable signal to Receive Fractional DS1 Out-
put signal (RxFrTD_n) when the un-gaped Receive Serial Output Clock
(RxSerClk_n) is used to latch in Fractional DS1 Payload Data into the Terminal
Equipment.
217
B
IT
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38