XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 435

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
Two 96-byte buffers in shared memory are allocated for receive LAPD Controller to reduce the frequency of
microprocessor interrupts and alleviate the response time requirement for microprocessor to handle each
interrupt. There are no restrictions on the length of the message received. However, the 96-byte buffer is deep
enough to hold one entire LAPD path or test signal identification message.
The following section discuss how to configure the receive LAPD Controller to receive and extract MOS
messages.
13.2.4.1
This section describes how to configure the LAPD Controller Block to receive and extract MOS message in a
step-by-step basis.
The operation of the receive LAPD Controller is interrupt-driven. When an MOS message is receiving,
message octets are written to the next receive data link message buffer opposite to that last used. Each time
the receiving data link message buffer is filled, a RxEOT interrupt is issued if it is enabled. This process
continues until an ABORT sequence is received or an IDLE flag is received.
An interrupt is issued when one of the following conditions occurs and the corresponding interrupt enable bit is
set.
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13.2.4.1.1
The receive LAPD Controller can generate a couple of interrupts indicating the status of MOS message
received to the microprocessor. These are the Receive Start of Transfer (RxSOT) interrupt and the Receive
End of Transfer (RxEOT) interrupt.
To enable these interrupts, the Receive Start of Transfer Enable bit and the Receive End of Transfer Enable bit
of the Data Link Interrupt Enable Register (DLIER) have to be set. In addition, the HDLC Controller Interrupt
Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive Start of Transfer Enable bit and the Receive End of
Transfer Enable bit of the Data Link Interrupt Enable Register.
DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H)
N
The RxSOT is set when the beginning of a data link message is received (the first non-flag message).
The RxEOT is set when the end of a data link block is received.
The RxIDLE is set if an IDLE flag sequence (b01111110) is received on the data link after either an ABORT
sequence is received or a complete message is received.
The RxABORT is set when an ABORT sequence is received.
The FCS_ERR is issued when an erroneous frame check sequence is detected at the end of a message or
an idle flag is received that is not octet aligned.
UMBER
B
5
3
IT
Receive Start of
Transfer Enable
Transfer Enable
Receive End of
How to configure the Receive HDLC Controller Block to receive MOS message
Step 1: Enable receive MOS message interrupts
B
IT
N
AME
B
IT
R/W
R/W
T
YPE
0 - The Receive Start of Transfer interrupt is disabled.
1 - The Receive Start of Transfer interrupt is enabled.
0 - The Receive End of Transfer interrupt is disabled.
1 - The Receive End of Transfer interrupt is enabled.
415
B
IT
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38