XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 335

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XRT84L38IB

Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT84L38IB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REV. 1.0.1
RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H,
0X0CH)
For every received Sa bit that is determined to carry Data Link information, the Receive Overhead Output
Interface will supply a clock pulse, via the RxOHClk_n output pin, such that:
Figure 110
Output Interface module in E1 framing format mode.
F
IGURE
N
The Receive Overhead Output interface should update the data on the RxOH_n line before the rising edge of
RxOHClk_n.
The external Data Link equipment interfaced to the Receive Overhead Output Interface will sample and latch
the data on the RxOH_n line on the rising edge of RxOHClk_n.
UMBER
B
4
3
IT
RxMSync
RxOhClk
110. E1 R
Frame #
RxSerClk
RxSync
RxOhClk
RxSync
RxOh
below shows the timing diagram of the output signals associated with the E1 Receive Overhead
RxSer
Receive Sa5 Data
Receive Sa4 Data
RxOh
Link Select
Link Select
B
IT
ECEIVE
N
AME
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
O
VERHEAD
B
LSB
IT
R/W
R/W
T
YPE
O
Si
UTPUT
0 - The received Sa5 Nation bit is not extracted to the data link interface.
1 - The received Sa5 Nation bit is extracted to the data link interface.
0 - The received Sa4 Nation bit is not extracted to the data link interface.
1 - The received Sa4 Nation bit is extracted to the data link interface.
1
If Sa4, SA7 and Sa8 are selected.
I
NTERFACE
A
Channel 0
Sa4
Sa4
315
Sa5
Sa5 Sa6
T
Sa6
IMING
Sa7
Sa7
Sa8
Sa8
B
IT
MSB
D
ESCRIPTION
Channel 1
OCTAL T1/E1/J1 FRAMER
XRT84L38
LSB

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