XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 30
XRT84L38IB
Manufacturer Part Number
XRT84L38IB
Description
Network Controller & Processor ICs 8 Ch T1/E1 Framer
Manufacturer
Exar Corporation
Datasheet
1.XRT84L38.pdf
(453 pages)
Specifications of XRT84L38IB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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XRT84L38
OCTAL T1/E1/J1 FRAMER
TRANSMIT SERIAL DATA INPUT
(Framer Channel Number indicated by _n)
S
IGNAL
TxInClk_0
TxInClk_1
TxInClk_2
TxInClk_3
TxInClk_4
TxInClk_5
TxInClk_6
TxInClk_7
N
AME
AC26
AF21
AF10
P
AE6
B13
A22
F26
C6
IN
#
T
YPE
I
Transmit Input Clock Signal -- Transmit Framer _n (continued)
Transmit Back-plane Interface-H.100, 16.384 MHz Clock Mode
If TxMUXEN = 1 and TxIMODE[1:0] = 11 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking multiplexed data at a rate
of 16.384 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals
running at 16.384 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not
required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and
latched into Transmit back-plane interface using clock edge of TxInClk_0 via
TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-
plexed and latched into Transmit back-plane interface using clock edge of
TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-
plexed into 8 channels from the serial inputs of Channel 0 and 4.
E1 Mode:
Transmit Back-plane Interface-2.048 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 01 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 2.048
Mbit/s. The TxInClk_n signal will be an Input clock signal running at 2.048
MHz.
Transmit Back-plane Interface-4.096 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 10 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 4.096
Mbit/s. The TxInClk_n signal will be an Input clock signal running at 4.096
MHz.
Transmit Back-plane Interface-8.192 MHz Clock Mode
If TxMUXEN = 0 and TxIMODE[1:0] = 11 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking data at a rate of 8.192
Mbit/s. The TxInClk_n signal will be an Input clock signal running at 8.192
MHz.
Transmit Back-plane Interface-Multiplexed at 16.384 MHz Clock Mode
If TxMUXEN = 1 and TxIMODE[1:0] = 01 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking multiplexed data at a rate
of 16.384 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals
running at 16.384 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not
required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and
latched into Transmit back-plane interface using clock edge of TxInClk_0 via
TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-
plexed and latched into Transmit back-plane interface using clock edge of
TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-
plexed into 8 channels from the serial inputs of Channel 0 and 4.
Transmit Back-plane Interface-HMVIP, 16.384 MHz Clock Mode
If TxMUXEN = 1 and TxIMODE[1:0] = 10 in Transmit interface control register,
Transmit back-plane interface of Framer_n is taking multiplexed data at a rate
of 16.384 Mbit/s. TxInClk_0 and TxInClk_4 signals will be Input clock signals
running at 16.384 MHz. TxInClk_1, 2, 3 and TxInClk_5, 6, 7 signals are not
required. Transmit Payload data of Channel 0, 1, 2 and 3 are multiplexed and
latched into Transmit back-plane interface using clock edge of TxInClk_0 via
TxSer_0 input pin. Transmit Payload data of Channel 4, 5, 6 and 7 are multi-
plexed and latched into Transmit back-plane interface using clock edge of
TxInClk_4 via TxSer_4 input pin. Inside the Octal Framer, data will be de-multi-
plexed into 8 channels from the serial inputs of Channel 0 and 4.
10
D
ESCRIPTION
REV. 1.0.1
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