XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 214

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
When the Transmit Multiplex Enable bit is set to zero and the Transmit Interface Mode Select [1:0] bits are set to
01, the Transmit Back-plane interface of framer is running at a data rate of 2.048Mbit/s.
The interface consists of the following pins:
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The Transmit Back-plane interface is accepting data through TxSer_n at an E1 equivalent data rate of 2.048Mbit/
s. The local Terminal Equipment supplies a free-running 2.048MHz clock to the Transmit Input Clock pin of the
framer. The local Terminal Equipment also provides synchronized payload data at rising edge of the clock. The
Transmit High-speed Back-plane Interface of the framer then latches incoming serial data at falling edge of the
Transmit Input Clock. The local Terminal Equipment should pump in data grouped in 256-bit frame 8000 times
every second. Each frame consists of thirty-two octets as in E1. The local Terminal Equipment maps a 193-bit T1
frame into this 256-bit format as described below:
The mapping of T1 frame into E1 framing format is shown in the table below.
The Transmit Single-frame Synchronization input signal (TxSync_n) should pulse HIGH at the beginning (F-bit
position) of the 256-bit frame indicating start of the frame. By sampling the HIGH pulse on the Transmit Single-
frame Synchronization signal, the framer can position the beginning of a DS1 frame. It is responsibility of the local
Terminal Equipment to align the Transmit Single-frame Synchronization signal with serial data stream going into
the framer.
Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are
then processed by the framer and send to LIU interface. The local Terminal Equipment provides a free-running
1. The Framing (F-bit) is mapped into MSB of the first E1 Time-slot. The local Terminal Equipment will stuff
2. Payload data of T1 Time-slot 0, 1 and 2 are mapped into E1 Time-slot 1, 2 and 3.
3. The local Terminal Equipment will stuff E1 Time-slot 4 with eight "don't care" bits that would be ignored by
4. Following the same rules of Step 2 and 3, the local Terminal Equipment maps every three time-slots of T1
4.1.3.1
Data input (TxSer_n)
Transmit Serial Clock Input signal (TxSerClk_n)
Transmit Single-frame Synchronization Input signal (TxSync_n)
Transmit Input Clock (TxInClk_n)
Transmit Time-slot Indication clock (TxTSClk_n)
Transmit Time Slot indicator bits (TxTSb[4:0]_n)
E1
E1
E1
E1
T1
T1
T1
T1
the rest seven bits of the first octet with "don't care" bits that would be ignored by the framer.
the framer.
payload data into four E1 time-slots.
Don't Care Bits
Don't Care Bits
Don't Care Bits
T1 Transmit Input Interface - MVIP 2.048 MHz
TS16
TS24
F-Bit
TS0
TS8
T
ABLE
TS12
TS17
TS18
TS25
TS0
TS1
TS6
TS9
39: T
HE MAPPING OF
TS10
TS13
TS18
TS19
TS26
TS1
TS2
TS7
T1
TS14
TS19
TS20
TS27
TS11
TS2
TS3
TS8
194
FRAME INTO
Don't Care Bits
Don't Care Bits
Don't Care Bits
Don't Care Bits
TS12
TS20
TS28
TS4
E1
FRAMING FORMAT
TS13
TS15
TS21
TS21
TS29
TS3
TS5
TS9
TS10
TS14
TS16
TS22
TS22
TS30
TS4
TS6
REV. 1.0.1
TS11
TS15
TS17
TS23
TS23
TS31
TS5
TS7