XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 206

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0xn0H, 0x00H)
The Transmit Serial clock signal pin (TxSerClk_n) is output from the framer. The framer outputs a 1.544MHz
clock through this pin to the local Terminal Equipment. The Transmit Single-frame Synchronization signal and the
Transmit Multi-frame Synchronization signal are also automatically configured to be output signals.
The Transmit Single-frame Synchronization signal should pulse HIGH for one DS1 bit period (648ns) at the last
bit position of each DS1 frame. By triggering on the HIGH pulse on the Transmit Single-frame Synchronization
signal, the local Terminal Equipment can identify the end of a DS1 frame and should start inserting payload data
of the next DS1 frame to the framer.
The Transmit Multi-frame Synchronization signal should pulse HIGH for one DS1 bit period (648ns) at the last bit
position of the last frame of a DS1 multi-frame. By triggering on the HIGH pulse on the Transmit Multi-frame
Synchronization signal, the local Terminal Equipment can identify the end of a DS1 super-frame and should start
inserting payload data of the next DS1 multi-frame into the framer.
N
UMBER
B
3-2
IT
Frequency
B
OSCCLK
Select
IT
N
AME
B
IT
R/W
T
YPE
OSCCLK Frequency Select:
These two READ/WRITE bit-fields permit the user to select internal clock divid-
ing logic of the framer depending on the frequency of incoming oscillator clock
(OSCCLK). The frequency of internal clock used by the framer should be
12.352MHz.
00 - The framer will internally divide the incoming OSCCLK by one. Therefore,
the external oscillator clock applied to the OSCCLK pin should be 12.352MHz.
01 - The framer will internally divide the incoming OSCCLK by two. Therefore,
the external oscillator clock applied to the OSCCLK pin should be 24.704MHz.
10 - The framer will internally divide the incoming OSCCLK by four. Therefore,
the external oscillator clock applied to the OSCCLK pin should be 49.408MHz.
186
B
IT
D
ESCRIPTION
REV. 1.0.1