XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 282

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
The timing diagram of input signals to the framer when running at MVIP 2.048Mbit/s mode is shown in
Figure 70
(This interface mode is the same as running at 2.048 MHz. The only difference is that the Transmit Input Clock
runs two times faster at 4.096 MHz)
When the Transmit Multiplex Enable bit is set to zero and the Transmit Interface Mode Select [1:0] bits are set
to 10, the Transmit Back-plane interface of framer is running at a clock rate of 4.096MHz.
The interface consists of the following pins:
•
•
•
•
•
•
The Transmit Back-plane interface is still accepting data through TxSer_n at an E1 equivalent data rate of
2.048Mbit/s. However, the local Terminal Equipment supplies a free-running 4.096MHz clock to the Transmit
Input Clock pin of the framer. The local Terminal Equipment provides synchronized payload data at every other
rising edge of the Transmit Input Clock. The Transmit High-speed Back-plane Interface of the framer then
latches incoming serial data at every other falling edge of the clock.
Transmit Single-frame Synchronization input signal (TxSync_n) should pulse HIGH at the beginning of the
256-bit frame indicating start of the frame. By sampling the HIGH pulse on the Transmit Single-frame
Synchronization signal, the framer can position the beginning of an E1 frame. It is responsibility of the local
Terminal Equipment to align the Transmit Single-frame Synchronization signal with serial data stream going
into the framer.
F
6.1.3.2
IGURE
Data input (TxSer_n)
Transmit Serial Clock Input signal (TxSerClk_n)
Transmit Single-frame Synchronization Input signal (TxSync_n)
Transmit Input Clock (TxInClk_n)
Transmit Time-slot Indication clock (TxTSClk_n)
Transmit Time Slot indicator bits (TxTSb[4:0]_n)
TxSerClk
TxSerClk (INV)
TxSer
TxSync(input)
TxSync(input)
MVIP mode
TxChn[0]/TxSig
TxChClk
TxChn[1]/TxFrTD
TxChn[1]/TxFrTD
TxChClk
Note: The following signals are not aligned with the signals shown above. The TxChClk is derived from 1.544MHz transmit clock.
TxSyncFrd=0
TxSyncFrd=1
70. T
.
IMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT
E1 Transmit Input Interface - 4.096 MHz
F
Don't Care
Don't Care
Don't Care
Don't Care
1
2
3
4
5
A B
6
7
C
D
8
1
Don't Care
1
1
2
2
2
3
3
3
262
4
4
4
5
A B
5
5
6
6
6
C
7
7
7
D
8
8
8
1
Don't Care
2
3
4
5
A B
6
Don't Care
Don't Care
C
7
D
8
MVIP 2.048M
Don't Care
Don't Care
1
Don't Care
1
1
BIT
2
2
2
3
3
3
/
S
4
4
4
A B
REV. 1.0.1
5
5
5
6
6
6
C
7
7
7
D
8
8
8