XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 339

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
The CRC-6 Source Select bit of the Synchronization MUX Register (SMR) controls from where to input CRC-6
bits into the framer. The table below shows configurations of the CRC-6 Source Select bit of the
Synchronization MUX Register (SMR).
SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H)
The XRT84L38 T1/J1/E1 Octal Framer provides individual control of each of the twenty-four DS0 channels.
The user can apply data and signaling conditioning to raw DS1 payload data coming from the Terminal
Equipment on a per-channel basis.
The XRT84L38 framer can apply the following changes to raw DS1 PCM data coming from the Terminal
Equipment on a per-channel basis:
•
•
•
•
•
Configuration of the XRT84L38 framer to apply the above-mentioned changes to raw DS1 PCM data are
controlled by the Transmit Data Conditioning Select [3:0] bits of the Transmit Channel Control Register (TCCR)
of each DS0 channel.
The XRT84L38 framer can also replace the incoming raw DS1 PCM data from the Terminal Equipment with
pre-defined or user-defined codes. The XRT84L38 supports the following conditioning substitutions:
•
•
•
•
•
•
•
•
Once again, configuration of the XRT84L38 framer to replace raw DS1 PCM data with the above-mentioned
coding schemes are controlled by the Transmit Data Conditioning Select [3:0] bits of the Transmit Channel
Control Register (TCCR) of each DS0 channel.
9.3
N
All 8 bits of the input PCM data are inverted
The even bits of the input PCM data are inverted
The odd bits of the input PCM data are inverted
The MSB of the input PCM data is inverted
All input PCM data except the MSB are inverted
BUSY code - an octet with hexadecimal value of 0x7F
BUSY_TS code - an octet of pattern "111xxxxx" where "xxxxx" represents the timeslot number
VACANT code - an octet with hexadecimal value of 0xFF
A-law Digital Milliwatt code
u-law Digital Milliwatt code
IDLE code - an octet defined by the value stored in the User IDLE Code Register (UCR)
MOOF code - MUX-Out-Of-Frame code with hexadecimal value of 0x1A
PRBS code - an octet generated by the Pseudo-Random Bit Sequence (PRBS) Generator block of the
framer
UMBER
B
1
IT
How to Configure the Framer to Apply Data and Signaling Conditioning to DS1 Payload Data on
a Per-Channel Basis
CRC-6 Source
B
IT
Select
N
AME
B
IT
R/W
T
YPE
CRC-6 Source Select:
This READ/WRITE bit-field permits the user to determine where the CRC-
6 bits should be inserted.
0 - The CRC-6 bits are generated and inserted by the framer internally.
1 - If the framer is operating in normal 1.544Mbit/s mode, the CRC-6 bits
are generated by external equipment and passed through from the Trans-
mit Serial Data Input Interface block via the TxSer_n pin.
319
B
IT
D
ESCRIPTION
OCTAL T1/E1/J1 FRAMER
XRT84L38