XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 168

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
Data Link Interrupt Enable Register (DLIER) (Indirect Address = 0xnAH, 0x07H)
B
IT
Reserve
B
N
IT
0
UMBER
7
6
5
4
3
2
7
Reserved
Transmit Start of Transfer
Interrupt Enable
Receive Start of Transfer
Interrupt Enable
Transmit End of Transfer
Interrupt Enable
Receive End of Transfer
Interrupt Enable
Frame Check Sequence
Error Detection Interrupt
Enable
Transmit
Transfer
Interrupt
Start of
Enable
B
R/W
IT
0
6
B
IT
N
AME
Receive
Transfer
Interrupt
Start of
Enable
B
R/W
IT
0
5
B
IT
R/W
R/W
R/W
R/W
R/W
Transmit
Transfer
Interrupt
T
Enable
End of
YPE
B
R/W
IT
0
4
Transmit Start of Transfer Interrupt Enable:
When this bit is set to 0:
The Transmit Start of Transfer interrupt is disabled.
When this bit is set to 1:
The Transmit Start of Transfer interrupt is enabled.
Receive Start of Transfer Interrupt Enable:
When this bit is set to 0:
The Receive Start of Transfer interrupt is disabled.
When this bit is set to 1:
The Receive Start of Transfer interrupt is enabled.
Transmit End of Transfer Interrupt Enable:
When this bit is set to 0:
The Transmit End of Transfer interrupt is disabled.
When this bit is set to 1:
The Transmit End of Transfer interrupt is enabled.
Receive End of Transfer Interrupt Enable:
When this bit is set to 0:
The Receive End of Transfer interrupt is disabled.
When this bit is set to 1:
The Receive End of Transfer interrupt is enabled.
Frame Check Sequence Error Detection Interrupt Enable:
When this bit is set to 0:
The Frame Check Sequence Error Detection interrupt is dis-
abled.
When this bit is set to 1:
The Frame Check Sequence Error Detection interrupt is
enabled.
148
Receive End
of Transfer
Interrupt
Enable
B
R/W
IT
0
3
Sequence
Detection
Interrupt
Enable
Frame
Check
B
B
Error
R/W
IT
IT
0
D
2
ESCRIPTION
Sequence
Receive
Interrupt
ABORT
Enable
B
R/W
IT
0
1
IDLE Flag
Sequence
Interrupt
Receive
Enable
REV. 1.0.1
B
R/W
IT
0
0