XRT84L38IB Exar Corporation, XRT84L38IB Datasheet - Page 320

• Manufacturer Part Number: XRT84L38IB
• Description: Network Controller & Processor ICs 8 Ch T1/E1 Framer
• Manufacturer: Exar Corporation

Specifications of XRT84L38IB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT84L38
OCTAL T1/E1/J1 FRAMER
SECOND OCTET OF 16.384MBIT/S DATA STREAM
FOURTH OCTET OF 16.384MBIT/S DATA STREAM
SIXTH OCTET OF 16.384MBIT/S DATA STREAM
EIGHTH OCTET OF 16.384MBIT/S DATA STREAM
X
A
The Receive Single-frame Synchronization signal should pulse HIGH for two clock cycles (the last bit position
of the previous multiplexed frame and the first bit position of the next multiplexed frame) indicating frame
boundary of the multiplexed data stream. The Receive Single-frame Synchronization signal of Channel 0
pulses HIGH to identify the start of multiplexed data stream of Channel 0-3. The Receive Single-frame
Synchronization signal of Channel 0 pulses HIGH to identify the start of multiplexed data stream of Channel 0-
3. By sampling the HIGH pulse of the Receive Single-frame Synchronization signal, the Receive High-speed
Back-plane Interface of the framer can identify the beginning of a multiplexed frame and can start sending
payload data of that frame.
2. The Receive High-speed Back-plane Interface also multiplexed signaling bits with payload bits and sent
3. After the first octets of all four channels are sent, the Receive High-speed Back-plane Interface will start
Y
Y
: The signaling bit A of Channel Y
: The Xth payload bit of Channel Y
them together through the 16.384Mbit/s data stream.
When the Receive High-speed Back-plane Interface is sending the fifth payload bit of a particular channel,
instead of sending it twice, it inserts the signaling bit A of that particular channel. Similarly, the sixth
payload bit of a particular channels is followed by the signaling bit B of that channel; the seventh payload
bit is followed by the signaling bit C; the eighth payload bit is followed by the signaling bit D.
The following table illustrates how payload bits and signaling bits are multiplexed together into the
16.384Mbit/s data stream.
sending the second octets following the same rules of Step 1 and 2.
B
B
B
B
5
5
5
5
IT
IT
IT
IT
0
1
2
3
0
0
0
0
B
B
B
B
A
A
A
A
IT
IT
IT
IT
0
1
2
3
1
1
1
1
B
B
B
B
6
6
6
6
IT
IT
IT
IT
0
1
2
3
2
2
2
2
B
B
B
B
B
B
B
B
IT
IT
IT
IT
0
1
2
3
3
3
3
3
300
B
B
B
B
7
7
7
7
IT
IT
IT
IT
0
1
2
3
4
4
4
4
B
B
B
B
C
C
C
C
IT
IT
IT
IT
0
1
2
3
5
5
5
5
B
B
B
B
8
8
8
8
IT
IT
IT
IT
0
1
2
3
6
6
6
6
REV. 1.0.1
B
B
B
B
D
D
D
D
IT
IT
IT
IT
0
1
2
3
7
7
7
7