NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 114

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 41.
5.6.1
5.6.1.1
Table 42.
Intel
DS
114
®
6300ESB I/O Controller Hub
Interrupt Controller Core Connections (Sheet 2 of 2)
The Intel
through master controller interrupt input two. This means there are only 15 possible
interrupts for the Intel
Interrupts may individually be programmed to be edge or level, except for IRQ0, IRQ2
and IRQ8#.
Note that previous PIIXn devices internally latched IRQ12 and IRQ1 and required a port
60h read to clear the latch. The Intel
IRQ12 or IRQ1 (see bit 11 and bit 12 in General Control Register, D31:F0, offset D0h).
Interrupt Handling
Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts.
Interrupt Status Registers
IMR
8259
Slave
IRR
ISR
Bit
Interrupt Request Register. This bit is set on a low to high transition of the interrupt
line in edge mode, and by an active high level in level mode. This bit is set whether or
not the interrupt is masked. However, a masked interrupt will not generate INTR.
Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,
when an interrupt acknowledge cycle is seen, and the vector returned is for that
interrupt.
Interrupt Mask Register. This bit determines whether an interrupt is masked.
Masked interrupts will not generate INTR.
®
6300ESB ICH cascades the slave controller onto the master controller
Input
8259
0
1
2
3
4
5
6
7
Internal Real Time
Clock
Generic
Generic
Generic
PS/2 Mouse
Internal
Primary IDE cable
Secondary IDE Cable
Typical Interrupt
®
6300ESB ICH PIC.
Source
®
6300ESB ICH may be programmed to latch
Table 42
Internal RTC / MMT #1
IRQ9 via SERIRQ, SCI or TCO, PIRQx, Boot
Interrupt
IRQ10 via SERIRQ, SCI, or TCO, PIRQx
IRQ11 via SERIRQ, SCI, or TCO, PIRQx,
Multimedia Timer #2
IRQ12 via SERIR, SCI, or TCO, PIRQx
State Machine output based on processor FERR#
assertion. See
Not Supported via SERIRQ”
IRQ14 from input signal (primary IDE in legacy
mode only) or via SERIRQ PIRQx
IRQ15 from input signal (secondary IDE in legacy
mode only) or via SERIRQ, PIRQx
Description
defines the IRR, ISR and IMR.
Connected Pin / Function
Section 5.8.4, “Specific Interrupts
Order Number: 300641-004US
for more information.
Intel
®
6300ESB ICH—5
November 2007